Tech Stack

Description

You will design component units of the Reconfigurable Dataflow Unit ASICs for AI workload acceleration systems, working with architects and design teams to implement innovative hardware features. You will define microarchitecture specs, code and debug SystemVerilog RTL designs, and drive improvements using AI and automation.

Requirements

• Master's or PhD in Computer Engineering or Electrical Engineering
• Computer architecture and digital logic design knowledge
• Mastery of SystemVerilog for high-speed, high-performance ASICs
• Experience in digital logic synthesis and Static Timing Analysis (STA)
• Proficiency with linting, CDC, LEC tools, and hardware performance analysis

Responsibilities

• Define and document microarchitecture specifications for compute, memory, or networking subsystems
• Code, integrate, and debug SystemVerilog RTL designs through chip implementation lifecycle
• Meet Power, Performance, and Area (PPA) targets using advanced digital design techniques
• Work with design verification and physical design teams to converge designs
• Mentor junior design engineers on high-speed digital design techniques