Tech Stack

Description

As a Principal ASIC Design Engineer on the Starshield team, you will design digital ASICs and FPGAs for next-generation space and ground infrastructure, collaborating in a fast-paced environment focused on rapid iteration from design to operational capability.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science
• 10+ years of experience in RTL implementation and/or FPGA/ASIC development
• Experience solving problems including clock domain crossings and power optimization
• Experience with standard bus protocols (e.g., AXI, AHB) and embedded processors
• Scripting skills (Python, TCL) and EDA tools experience

Responsibilities

• Design digital ASICs and/or FPGAs for Starshield projects
• Evaluate architectural trade-offs based on features, performance, and system limitations
• Derive specifications and partition functions between hardware and software
• Define micro-architecture, implement RTL in Verilog/System Verilog, integrate and deliver synthesis/timing clean design
• Provide timing constraints and support physical implementation team