Tech Stack

Description

You will lead the discipline of layout at the technical level, working with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs. You'll determine chip floor plans, perform layout of custom RF and analog circuit blocks, and execute top-level layout integration and tape out.

Requirements

• Bachelor’s in electrical or computer engineering + 5 years IC layout experience OR 8+ years IC layout experience in lieu of degree
• Strong analog layout skills
• Experience in advanced node IC layouts (22nm, 16nm, 7nm, 5nm or below)
• Experience in layout of circuits up to 50GHz
• Experience with skill programming, shell scripting, Perl, Python, revision control, and Linux

Responsibilities

• Work with IC designers and chip leads to determine chip floor plan, including power/ground distribution and pad locations
• Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance
• Perform design rule checking, electrical rule checking, and layout versus schematic checks and resolve errors
• Perform top-level layout integration with ESD structures and pad assembly, and final tape out including density fill and DFM checks
• Work with EDA suppliers to trial new tools and features; generate guides and demos for layout technique improvements