Tech Stack

Description

You will lead the complete RTL-to-GDSII physical design flow for complex SoCs targeting advanced FinFET technologies, owning timing closure, PPA optimization, and collaboration with architecture, RTL, DFT, and packaging teams. You'll also manage external design partners and drive tool/flow decisions to ensure first-pass silicon success for next-generation satellite and space systems.

Requirements

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience in ASIC physical design for high-performance SoCs
• Proven end-to-end expertise in RTL-to-GDSII flows using Synopsys, Cadence, or Siemens tools
• Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation
• Experience with advanced FinFET process nodes

Responsibilities

• Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place and route, clock tree synthesis, STA, physical verification, and sign-off
• Develop physical design methodologies and automation to optimize PPA
• Collaborate with front-end and verification teams for clean handoffs and timing closure
• Manage external physical design partners and service vendors
• Support chip bring-up and debug with post-silicon and test teams