Tech Stack

Description

You will own behavioral modeling for mixed-signal SoCs used in advanced satellites, driving verification methodology and collaborating with RF, analog, and digital teams to ensure successful tapeout.

Requirements

• Experience developing behavioral models for analog and mixed-signal IP.
• Proficiency with Verilog, Verilog-AMS, or SystemVerilog.
• Experience with mixed-signal co-simulation and testbench development.
• Familiarity with UVM-based digital verification environments.
• Ability to collaborate with analog/RF designers and digital/verification teams.

Responsibilities

• Develop behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, etc.) using Verilog, Verilog-AMS, or SystemVerilog.
• Create regression infrastructure and mixed-signal testbenches for co-simulation.
• Integrate AMS models into UVM-based digital verification environments.
• Define and build mixed-signal verification methodology for top-level SoC and subsystem verification.
• Support architectural exploration through early-phase modeling and system-level simulations.