🛠 Tech Stack

💼 About This Role

You'll implement complex digital blocks in advanced tech nodes, driving timing closure and power integrity for high-performance ASICs. Working alongside world-class engineers, you'll define system optimizations pioneering new photonics challenges. This role offers hands-on impact on cutting-edge AI hardware at a $4.4B valued startup.

🎯 What You'll Do

• Implement digital blocks from synthesis through physical verification
• Understand and debug timing constraints, derates, and margins
• Build and customize power grid for power integrity goals
• Debug DRC/LVS and implement Functional/Timing ECOs

📋 Requirements

• Bachelor's in Electrical Engineering or Computer Engineering
• At least 8+ years of industry experience as a Physical Design Engineer
• Completed blocks or top level physical design for taped-out ASICs or mixed signal chips
• Thorough knowledge of timing closure and LVS/DRC closure

✨ Nice to Have

• Master's in Electrical Engineering or Computer Engineering
• Hands-on experience with Cadence tools
• Tape-out experience on 3nm designs

🎁 Benefits & Perks

• 🏥 Comprehensive Health Care Plan (Medical, Dental, Vision)
• 💰 Retirement Savings Matching Program
• 🏖️ Generous Time Off (Vacation, Sick, Public Holidays)
• 👶 Paid Family Leave
• 🚗 Commuter Benefits

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter screen· 30 min
2. 2Technical interview· 60 min
3. 3Onsite interviews· 240 min

🚩 Heads Up

• Mentions manual layout and silicon photonics layout which may be outside typical PD scope