Tech Stack

Description

You will develop next-generation ASICs for SpaceX's Starlink network, implementing and optimizing DFT architectures, integrating DFT IPs, running ATPG, and performing post-silicon bringup and debug.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, or physics
• 5+ years of experience in semiconductor DFT engineering, post-silicon validation, or production testing
• Experience with Siemens Tessent workflows
• Hands-on experience with ATE platforms (e.g., Teradyne, Advantest)
• Ability to work extended hours and weekends as needed

Responsibilities

• Implement and optimize DFT architectures using Siemens Tessent tools (scan, compression, memory BIST, logic BIST)
• Integrate and verify DFT IPs and fabrics within subsystems
• Set up and run ATPG for stuck-at, transition, and path delay fault models
• Run and debug gate-level simulations (non-timing and SDF annotated)
• Create and validate DFT patterns for post-silicon bringup and ATE debug