🛠 Tech Stack

💼 About This Role

You'll own physical implementation for OLIX's next-generation accelerator silicon, from floorplanning to tape-out. You'll partner with circuit and digital teams to deliver high-performance analog and mixed-signal blocks. This role offers the chance to define layout methodology for breakthrough AI hardware and work on advanced CMOS FinFET nodes.

🎯 What You'll Do

• Execute full-custom analog/mixed-signal layouts in advanced CMOS FinFET nodes.
• Own floor-planning, power-grid, shielding, and signal-integrity for high-speed blocks.
• Lead block- and chip-level AMS integration with ESD/latch-up strategy.
• Drive physical-verification, parasitic-extraction, and EM/IR-drop sign-off.

📋 Requirements

• 8+ years of full-custom analog/mixed-signal IC layout experience.
• 3+ taped-out products with high-speed analog content (multi-GHz bandwidth).
• Expert command of Cadence Virtuoso platform (Layout XL, Schematic XL, ADE).
• Proficiency in physical-verification (Calibre or Pegasus/PVS) and parasitic extraction.

✨ Nice to Have

• Tape-out experience at 7nm or below with multi-patterning.
• Advanced PCell development for on-chip passives.
• Familiarity with coherent optical links or photonic-electronic co-design.

🎁 Benefits & Perks

• 💰 Competitive Salary: $365,000+
• 🏠 Living-Local Bonus: $36k annual if within 20 minutes of office.
• 🌴 33 days PTO including US federal holidays.
• 🏥 Healthcare Coverage: Multiple plans including family coverage.
• 📈 Equity & Ownership: Meaningful stock options.

📨 Hiring Process

Estimated timeline: 1-3 weeks · AI estimate

1. 1Recruiter Phone Screen· 30 min
2. 2Technical Interview· 60 min
3. 3Hiring Manager Interview· 45 min