🛠 Tech Stack

💼 About This Role

You'll own full-chip physical verification for next-gen silicon powering Starlink satellites. Your work will directly enable global broadband connectivity from space.

🎯 What You'll Do

• Own and execute full-chip DRC, LVS, ESD, PERC signoff
• Develop and optimize physical verification flows for advanced nodes
• Debug and resolve complex DRC/LVS violations across hierarchical designs
• Drive tapeout readiness coordinating with block, top-level, and IP teams

📋 Requirements

• Bachelor's degree in EE, CE, or CS
• 5+ years ASIC or physical design flow development experience

✨ Nice to Have

• SOC top-level physical design flow experience
• IP integration expertise (memories, I/O, SerDes, DDR)
• Hands-on proficiency with Calibre, ICV, or Pegasus

🎁 Benefits & Perks

• 🚀 Work on Starlink space-grade silicon
• 🏥 Health insurance including medical, dental, vision
• 💰 Stock options and performance bonuses
• 📚 Tuition reimbursement for continued education
• 🍔 Free lunch and snacks on campus

📨 Hiring Process

Estimated timeline: 4-6 weeks · AI estimate

1. 1Recruiter Call· 30 min
2. 2Technical Phone Screen· 60 min
3. 3Onsite Interview (4-5 rounds)· 4 hours

🚩 Heads Up

• ITAR requirement limits applicants to US citizens/ permanent residents only
• Extended hours / weekends expected to meet milestones