🛠 Tech Stack

💼 About This Role

You'll lead the backend physical design flow for advanced ASICs, from synthesis to GDSII. Your work will directly enable hyper-scaled IoT solutions in space. You'll collaborate across teams to deliver cutting-edge semiconductor designs.

🎯 What You'll Do

• Manage end-to-end backend physical design flow from floorplanning to routing.
• Optimize layout for power, timing closure, and area.
• Perform Static Timing Analysis and drive timing closure.
• Ensure DRC/LVS compliance using industry-standard tools.

📋 Requirements

• 5+ years in digital backend design with successful P&R and tape-out.
• Proficiency with Cadence Innovus or Synopsys ICC2.
• Strong knowledge of timing analysis and clock tree synthesis.
• Scripting experience with TCL or Python for tool automation.

✨ Nice to Have

• Bachelor's or Master's degree in Electrical Engineering or related field.
• Experience with advanced process nodes like 7nm or 5nm.
• Familiarity with IR drop analysis and EM checks.