🛠 Tech Stack

💼 About This Role

You'll define and implement verification plans, build test benches, and drive closure on design quality. You'll collaborate with cross-functional teams to ensure highest design quality in block/IP/SoC verification. Debug and resolve functional failures while working with Design, Model, Emulation, and Silicon validation teams.

🎯 What You'll Do

• Define and implement block/IP/SoC verification plans
• Build verification test benches for block/IP/sub-system/SoC
• Develop functional tests based on verification test plan
• Debug and resolve functional failures with Design team

📋 Requirements

• Bachelor's in Electrical Engineering, Computer Science or related field
• 3+ years experience in block/IP/SoC verification with SystemVerilog/UVM
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell)
• Experience architecting and implementing Design Verification infrastructure

✨ Nice to Have

• Master's in Electrical Engineering, Computer Science or related field
• Experience developing UVM verification environments from scratch
• Experience with high-speed interfaces like PCIe, UCIe, DDR

📨 Hiring Process

[email protected]