Tech Stack

Description

You will verify custom silicon designs for high-power satellites, working on block-level, subsystem-level, and full-chip verification using SystemVerilog/UVM and formal methods.

Requirements

• Experience with ASIC design verification
• Proficiency in SystemVerilog and UVM
• Knowledge of assertion-based and formal verification methodologies
• Collaboration with architecture, RTL, DFT, firmware, and silicon validation teams

Responsibilities

• Develop verification plans for block, subsystem, and full-chip levels
• Build SystemVerilog/UVM test benches (agents, monitors, scoreboards, checkers, coverage models)
• Write SystemVerilog Assertions (SVA) and integrate formal verification