🛠 Tech Stack

💼 About This Role

You'll lead a team to verify digital subsystems of high-speed mixed-signal ASICs, ensuring first-silicon success and on-schedule delivery. You'll own end-to-end verification strategy from architecture through mass production, driving cross-functional alignment and execution speed.

🎯 What You'll Do

• Lead end-to-end verification of digital subsystems using UVM and formal methods
• Define verification plans, sign-off criteria, and silicon-correlation strategies
• Manage and mentor a team of 6–12 verification engineers across sites
• Drive cross-functional alignment with design, analog, firmware, and test teams

📋 Requirements

• 10+ years of digital ASIC verification experience
• At least 3 full product cycles from spec to high-volume production
• Strong expertise in SystemVerilog/UVM, constrained-random verification, and formal verification
• Proven track record of first-silicon success on complex mixed-signal ASICs

✨ Nice to Have

• Experience with mixed-signal verification and real-number modeling
• Familiarity with emulation/FPGA prototyping
• Previous line management experience

🎁 Benefits & Perks

• 💰 Competitive Salary: $388,000+
• 📈 Equity & Ownership: meaningful stock options
• 🏡 Living-Local Bonus: $36k annual if within 20 minutes of office
• 🌴 Time Off: 33 days PTO including holidays
• 🏥 Healthcare: multiple plans including family coverage, HSA, dental, vision

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Screen· 30 min
2. 2Technical Interview· 60 min
3. 3Manager Interview· 45 min
4. 4Onsite Interview· 4 hours