🛠 Tech Stack

💼 About This Role

You'll help design microarchitecture and implement logic in Verilog at Etched, the company building the world's first transformer-specific AI inference ASIC. You'll contribute to RTL block development and participate in the full design cycle from microarchitecture to synthesis. You'll work on cutting-edge machine learning architectures and receive direct mentorship from industry leaders.

🎯 What You'll Do

• Design microarchitecture and implement logic in Verilog
• Contribute to RTL block development
• Participate in the full design cycle
• Work with cutting-edge ML architectures

📋 Requirements

• Progress towards a Bachelor's, Master's, or PhD in EE, CE, or related field
• Familiarity with high-speed digital logic
• Exposure to ASIC or SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python

✨ Nice to Have

• Familiarity with transformer models and machine learning
• Familiarity with numerical representations and functions
• Ability to program with Python or another scripting language

🎁 Benefits & Perks

• 💰 Generous housing support for those relocating
• 🍽️ Daily lunch and dinner in office
• 🧑‍🏫 Direct mentorship from industry leaders
• 🚀 Work on cutting-edge AI hardware

📨 Hiring Process

12-week paid internship (June - August 2026), based at our office in San Jose, CA.

[email protected]