Tech Stack

Description

You will design digital ASICs and FPGAs for Starshield projects, evaluate architectural trade-offs, define micro-architecture, implement RTL in Verilog/System Verilog, and work closely with verification and physical implementation teams to deliver clean designs. You'll also participate in silicon bring-up and validation, supporting U.S. National Security programs.

Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science
• 5+ years experience in RTL implementation and/or FPGA/ASIC development
• Experience with clock domain crossings and power optimization
• Experience with standard bus protocols (e.g., AXI, AHB)
• Scripting skills (Python, TCL)

Responsibilities

• Design digital ASICs and/or FPGAs for Starshield projects
• Evaluate architectural trade-offs based on features, performance, and system limitations
• Derive specifications and partition functions between hardware and software
• Define micro-architecture, implement RTL in Verilog/System Verilog, and deliver verified, synthesis/timing-clean design
• Provide timing constraints and support physical implementation team