Tech Stack

Description

You will design digital ASICs and FPGAs for Starlink projects, evaluating architectural trade-offs and implementing RTL in Verilog/SystemVerilog. Collaborate with cross-disciplinary teams to deliver cutting-edge chips for space and ground infrastructure, expanding the performance and capabilities of the Starlink network.

Requirements

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 10+ years of experience in RTL implementation and/or FPGA/ASIC development
• Experience solving problems including clock domain crossings and power optimization
• Experience developing complex ASICs and with multicore CPU subsystem design
• Experience with standard bus protocols (e.g., AXI, AHB) and EDA tools (HDL simulators, lint tools, FPGA tools)

Responsibilities

• Design digital ASICs and/or FPGAs for Starlink projects
• Evaluate architectural trade-offs based on features, performance requirements, and system limitations
• Define micro-architecture, implement RTL in Verilog/SystemVerilog, integrate at top level, and deliver fully verified, synthesis/timing clean design
• Work closely with verification team to ensure all aspects of design are covered and verified
• Provide timing constraints for IPs and support physical implementation team (synthesis, timing closure, formality check), participate in silicon bring-up and validation