23h ago

Senior Static Timing Analysis (STA) Methodology Engineer

Saratoga, CA

โœจ $180k-$250k / yearest.

full-timeseniortelecom

๐Ÿ›  Tech Stack

๐Ÿ’ผ About This Role

You'll lead cross-functional timing closure for advanced SoCs at a space-based IoT startup. You'll develop and enhance STA methodologies across the full RTL-to-GDS flow, driving signoff correlation and closure. This role offers the chance to deploy ML-assisted techniques and work on cutting-edge low-earth orbit satellite systems.

๐ŸŽฏ What You'll Do

  • Lead cross-functional efforts to solve complex timing challenges across multiple IPs and projects.
  • Architect and optimize production STA flows using industry-standard EDA tools.
  • Drive signoff correlation and closure using PrimeTime and related tools.
  • Develop and maintain scalable CAD utilities and STA flow components.

๐Ÿ“‹ Requirements

  • BS/MS in Electrical or Computer Engineering or equivalent experience.
  • 8+ years of industry experience in STA and timing methodology at advanced nodes.
  • Deep knowledge of STA tools including noise, crosstalk, OCV, AOCV, POCV, and LVF analysis.
  • Fluency with PrimeTime and related signoff tools (PT-SI, PTPX, PT-ECO).

โœจ Nice to Have

  • Experience with 7nm, 5nm, or below advanced process nodes.
  • Familiarity with low-power design methodologies (DVFS, power gating).
  • Exposure to interface protocol timing (DDR, PCIe, USB, SerDes).

๐ŸŽ Benefits & Perks

  • ๐Ÿš€ Work on cutting-edge space technology
  • ๐Ÿ’ก Innovative startup environment
  • ๐ŸŒ Hyper-scaled IoT solutions

๐Ÿ“จ Hiring Process

Estimated timeline: 2-4 weeks ยท AI estimate

  1. 1Recruiter Screenยท 30 min
  2. 2Technical Interviewยท 60 min
  3. 3Team Interviewยท 45 min
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