Tech Stack

Description

You will create test plans and write UVM/SystemVerilog code to verify complex IPs for interconnectivity in SoC and multi-chiplet systems. Collaborate with design and software teams on test benches, debug, and coverage. Your work directly enables innovative chip design solutions.

Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or Computer Science
• 8+ years hands-on experience in block-level/IP-level/SoC-level verification
• Proficiency in Verilog and SystemVerilog
• Deep experience with UVM-based test benches
• Familiarity with EDA tools for simulation and debug

Responsibilities

• Create test plans for highly configurable IPs for interconnectivity in SoC, chiplet, or multi-chiplet systems
• Write UVM/SystemVerilog code to implement test plans, checkers, and scoreboards
• Collaborate with software teams to define and implement configurable test benches
• Work with design teams on test plans, failure debug, and coverage