Tech Stack

Description

You will own RTL to GDS physical implementation flows for high-performance designs, collaborate with micro-architects on power and area trade-offs, and develop methodologies to optimize physical design for chiplets and multi-die systems.

Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or related field
• Experience in all aspects of physical design including synthesis, floor planning, place and route, timing power closure, EM/IR, PDV
• Experience with synthesis, place route, static timing analysis, and PDV tools
• Experience with Synopsys Design Compiler, PrimeTime, ICC, Fusion Compiler
• Good knowledge of high-performance and low-power microarchitecture and logic design principles

Responsibilities

• Own RTL to GDS physical implementation flows (synthesis, floor-planning, place and route, clock tree synthesis, timing power closure, EM/IR, PDV, final PD sign off)
• Own physical design implementation of high-performance designs from block to system level
• Collaborate with micro-architects to explore performance, power, and area trade-offs
• Perform physical implementation feasibility studies and develop methodologies for best PPA
• Perform physical design validation (PDV) for timing, power, EM/IR, DRC, LVS