🛠 Tech Stack

💼 About This Role

You'll own signal and power integrity for a transformer-purposed AI accelerator across silicon, package, and board. Your work will enable 10x higher performance over GPUs through cutting-edge 2.5D/3D packaging. You'll collaborate with cross-functional teams to push the limits of power delivery and high-speed signaling.

🎯 What You'll Do

• Perform SI/PI analysis and optimization of 2D/2.5D/3D packages
• Drive SI requirements into interposer/substrate layout (112G/224G routing)
• Own PDN design and decoupling strategy across substrate and interposer
• Manage ball map / C4 / BGA pin assignment from soft to final freeze

📋 Requirements

• Bachelor's or Master's in EE or related field
• 8+ years of SI/PI experience on high-performance platforms
• Proven experience defining and closing PDN for high-power silicon
• Hands-on expertise with ANSYS HFSS / SIwave, Cadence Sigrity, or Keysight ADS

✨ Nice to Have

• Familiarity with full RTL-to-GDSII context and PDN interactions
• Experience with multi-die, 2.5D, or 3D packaging signoff
• Startup experience or comfort in fast-paced environments

🎁 Benefits & Perks

• 🩺 Medical, dental, and vision with generous premium coverage
• 💰 $500/month credit for waiving medical benefits
• 🏠 $2k/month housing subsidy for living near office
• 🚚 Relocation support for moving to San Jose
• 🍽️ Daily lunch and dinner in the office

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Screen· 30 min
2. 2Technical Interview· 60 min
3. 3Onsite Interview· 4-6 hours