🛠 Tech Stack

💼 About This Role

You'll join a team developing cutting-edge multi-core in-memory compute SoCs, gaining hands-on experience across all stages of ASIC Physical Design. You'll support tasks from RTL to GDS, including synthesis, timing analysis, and physical verification. This role offers the chance to shape a fast-growing, international AI company.

🎯 What You'll Do

• Support synthesis, floorplanning, place and route, extraction, and timing analysis
• Participate in constraint generation, timing analysis, and optimization
• Apply clock tree synthesis (CTS) techniques
• Integrate IPs including memories, I/Os, and embedded processors

📋 Requirements

• 1-5 years of experience in Physical Design
• BSc or MSc in Electrical & Electronic Engineering or related
• Understanding of ASIC design flow (RTL to GDS)
• Experience with EDA tools like Fusion Compiler or Innovus

✨ Nice to Have

• Experience with device physics, spice simulation, analogue design
• Interest in AI hardware or compute architecture

🎁 Benefits & Perks

• 🏖️ Flexible working including hybrid options
• 💰 Attractive compensation including pension and insurance
• 📈 Company share options
• 🌍 Relocation support to Eindhoven
• 🎓 Open culture with continual innovation

🚩 Heads Up

• Mentions both intern and 1-5 years experience, role may be ambiguous
• Title senior but requirements up to 5 years, could be mismatched