🛠 Tech Stack

💼 About This Role

You'll design digital ASICs and FPGAs for Starshield, a program leveraging SpaceX's Starlink technology for national security. You'll derive specifications, implement RTL, and support silicon bring-up in a fast-paced environment. Iterate rapidly to deliver operational capability at lightning pace.

🎯 What You'll Do

• Design digital ASICs and FPGAs for Starshield projects.
• Evaluate architectural trade-offs and derive specifications.
• Implement RTL in Verilog/System Verilog and deliver synthesis/timing clean design.
• Support physical implementation, silicon bring-up, and validation.

📋 Requirements

• Bachelor's degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in RTL implementation or FPGA/ASIC development.
• Experience with clock domain crossings and power optimization.
• Experience with standard bus protocols (e.g., AXI, AHB).

✨ Nice to Have

• Experience developing complex ASICs.
• Experience with multicore CPU subsystem design.
• Scripting skills (Python, TCL).

🎁 Benefits & Perks

• 💰 Base salary $160k-$225k with potential 10% clearance differential.
• 📈 Long-term incentives including stock options and purchase plan.
• 🏥 Comprehensive medical, vision, dental coverage.
• 🏖️ 3 weeks paid vacation plus 10+ holidays.
• 👶 Paid parental leave and 401(k) retirement plan.

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Screen· 30 min
2. 2Technical Interview· 60 min
3. 3Onsite Interview· 4 hours

🚩 Heads Up

• Requires long hours and weekends as necessary
• ITAR restrictions limit applicants to US citizens/permanent residents only