Tech Stack

Description

You will develop cutting-edge FPGAs and ASICs for deployment in space and ground infrastructure, enabling global connectivity through the Starlink network. You'll work on micro-architecture, RTL implementation, and support silicon bring-up alongside cross-disciplinary teams.

Requirements

• Bachelor's degree in EE, CE, or CS
• 5+ years of experience in RTL implementation
• Experience with clock domain crossings and power optimization
• ASIC/SoC system integration experience
• Scripting skills (Python, TCL, etc.)

Responsibilities

• Evaluate architectural trade-offs based on features, performance, and system limitations
• Define micro-architecture, implement RTL in Verilog/SystemVerilog, integrate at top level
• Work with verification team to ensure full design coverage and verification
• Provide timing constraints and support physical implementation (synthesis, timing closure)
• Participate in silicon bring-up and validation