🛠 Tech Stack

💼 About This Role

You'll perform behavioral channel simulation and analysis of high-speed wireline SERDES systems supporting 100G+ PAM4 standards. You'll contribute to system architecture definition and develop simulation and debugging tools. This role combines deep theoretical understanding with hands-on optimization using machine learning techniques.

🎯 What You'll Do

• Model and analyze analog/mixed-signal blocks like FFE, CTLE, DFE, CDRs
• Develop simulation and debugging tools for validation teams
• Design adaptation algorithms for advanced equalization techniques
• Conduct sensitivity analysis and regression simulations

📋 Requirements

• Master's or PhD in Electrical Engineering or related field
• 5+ years of experience in SERDES system design or modeling
• Strong experience modeling FFE, CTLE, DFE, CDR and transmitter architectures
• Proficiency in MATLAB, C/C++, Python, Tcl, or Perl

✨ Nice to Have

• Experience with IBIS-AMI modeling
• Familiarity with PCI-SIG, IEEE 802.3, OIF standards

🎁 Benefits & Perks

• 💰 Base salary $115K-$225K depending on experience
• 📈 RSUs, short-term incentives, ESPP
• 🏥 Comprehensive health coverage, HSA, WSA
• 🏖️ Flexible paid vacation and holidays
• 👶 Parental leave top-up program

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Phone Screen· 30 min
2. 2Technical Interview· 60 min
3. 3System Design Interview· 60 min
4. 4Hiring Manager Interview· 45 min