🛠 Tech Stack

💼 About This Role

You'll lead the design and build of UVM-based verification environments for complex, safety-critical FPGA systems used in aerospace applications. Your core impact will be owning verification strategy, from testbench architecture to coverage closure, while guiding and mentoring engineering teams. This role stands out for its hands-on technical leadership with real-world mission-critical impact.

🎯 What You'll Do

• Lead development of SystemVerilog / UVM verification environments for FPGA designs
• Build and improve testbenches, agents, scoreboards, monitors, and sequences
• Define verification strategy, test plans, and coverage goals
• Drive functional, code, and assertion coverage closure

📋 Requirements

• 8–12+ years of experience in FPGA or ASIC verification
• Strong hands-on experience with SystemVerilog and UVM
• Experience building UVM testbenches and reusable verification environments
• Background in simulation, debugging, and coverage-driven verification

✨ Nice to Have

• Experience with emulation tools (Siemens Veloce, Palladium, etc.)
• Knowledge of high-speed interfaces or communication protocols
• Experience with DOORS or requirements traceability

🎁 Benefits & Perks

• 💰 $5,000 Sign-On Bonus included
• 🏥 Comprehensive medical/dental/life/disability coverage
• 🏖️ Flexible remote work with people-first culture
• 📈 401(k) with employer match
• 📚 Professional development and certification assistance

📨 Hiring Process

Estimated timeline: 2-4 weeks · AI estimate

1. 1Recruiter Screen· 30 min
2. 2Technical Interview· 60 min
3. 3Hiring Manager Interview· 45 min