You'll own the full sales cycle for **mid-market construction companies** running projects in the $50M–$150M range. You'll sell a **differentiated AI-powered schedule optimization platform** to an industry hungry for better tools. You'll collaborate with marketing, solutions, and customer success to close deals and build long-term relationships.

Alice Technologies

Construction simulation software

Job Details: Job Description: Intel’s AI SoC organization is driving innovation in next-generation ASICs for AI applications across edge and cloud. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs using advanced formal methods. This position offers the opportunity to work on cutting-edge technology and shape verification strategies for AI SoCs. Key Responsibilities Own formal verification strategy and execution for complex SoC IP blocks and subsystems. Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and industry-standard formal tools. Write and review formal properties, constraints, and coverage goals to achieve exhaustive verification. Collaborate with design and simulation teams to identify corner cases and complement dynamic verification. Drive formal sign-off, including convergence analysis and coverage closure. Contribute to pre-silicon verification, chip bring-up, and post-silicon debug support. Mentor junior engineers and establish best practices for formal verification methodology Additional Responsibilities Define and develop scalable, reusable verification plans for block, subsystem, and SoC levels. Execute verification plans and run emulation and system simulation models to validate design, analyze power/performance, and uncover bugs. Debug and root-cause issues in the presilicon environment; implement corrective measures. Collaborate with architects, RTL developers, and physical design teams to improve verification of complex features. Document test plans and lead technical reviews with design and architecture teams. Incorporate and execute security verification activities within regression and debug tests. Maintain and enhance existing functional verification infrastructure and methodology . Apply learnings from post-silicon validation to improve coverage and quality for future products. Qualifications: Minimum Qualifications Basic Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with 10+ years of related experience. • 7+ years of experience in ASIC/SoC verification with at least 3+ years focused on formal verification. Preferred Qualifications • Expertise in formal verification methodologies and tools (e.g., JasperGold, VC Formal, Questa Formal). • Strong knowledge of System Verilog Assertions (SVA) and property-based verification. • Deep understanding of digital design concepts, clock domain crossings, and low-power design techniques. • Familiarity with UVM-based simulation environments and how formal complements dynamic verification. • Scripting skills (Python, TCL, Perl) for automation and flow optimization. • Ability to lead projects, work cross-functionally, and deliver under tight schedules. • Strong analytical skills, attention to detail, and a collaborative mindset. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Austin Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: Do Something Wonderful! Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Who You Are We are seeking a highly motivated senior CPU verification engineer to join our design team. In this role, you will be responsible for driving and executing the functional correctness of CPU logic designs through rigorous pre-silicon verification methodologies. Key Responsibilities: Lead, drive, develop and execute comprehensive verification plans to validate CPU logic against architectural specifications. Able to build scalable UVM-based testbenches from and define robust functional coverage models. Run system-level simulations to uncover design bugs and ensure functional integrity. Debug and root-cause issues in the pre-silicon environment; implement corrective actions to resolve test failures. Collaborate closely with CPU architects and RTL designers to verify complex architectural and microarchitectural features. Document verification strategies and lead technical reviews with design and architecture teams. Maintain and enhance existing verification infrastructure and methodologies. Contribute to the definition and refinement of CPU architecture and microarchitecture features. Excellent analytical and debugging skills, with a creative approach to problem-solving. Ability to define and implement validation strategies based on architectural and design insights. Qualifications: You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications The candidate must have a Bachelor's Degree in Electrical/Electronic Engineering or Computer Engineering or any STEM related education with at least 4+ years of relevant experience -OR- Master's Degree in Electrical/Electronic Engineering or Computer Engineering or any STEM related education with at least 3+ years of relevant experience. 2+ years of experience in digital logic design, including instruction set execution, ALUs, control units, registers, memory, and system buses. 2+ years of experience in developing UVM-based testbenches for reusable and scalable verification environments. 2+ years of experience in at least one scripting language (e.g., Python, Perl, or Tcl), C++, and System Verilog. Preferred Qualifications Experience with RTL development Use of AI agents in Verification Proficiency with C/C++, System Verilog coding and debug Knowledge and experience with x86 or any other computer architectures Familiarity with version control software (GIT). Experience with Synopsys simulators Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, Oregon, Hillsboro Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: We are seeking an experienced Director of Analog Design & Infrastructure Design Automation to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs. The ideal candidate combines deep analog/mixed-signal design flow expertise with strong infrastructure leadership and disciplined configuration/data management practices. Key Responsibilities 1. Analog Design Environment & Flow Management Own and maintain analog and mixed-signal design flows using platforms such as Virtuoso and Custom Compiler. Manage PDK integration, validation, and controlled release in collaboration with foundries. Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC, PEX, EM/IR). Support simulation environments including Spectre, HSPICE, Monte Carlo, corner, and reliability analysis. Drive automation and methodology improvements to reduce turnaround time and increase design robustness. 2. Infrastructure & Compute Management Oversee Linux-based DA infrastructure including compute farms, storage systems, and license servers (FlexLM). Manage LSF/grid environments and job scheduling systems. Ensure scalability, system monitoring, high availability, and performance optimization. Partner with IT on hardware lifecycle planning, cloud integration, and disaster recovery. Maintain secure, access-controlled design environments aligned with IP protection policies. 3. Design Data, Manifest & Configuration Management Design Data Governance Manage large-scale analog design libraries, hierarchical database structures, and technology libraries. Define backup, archival, and retention policies for tapeout-critical data. Implement data integrity validation and corruption prevention controls. Oversee distributed storage systems optimized for EDA workloads. Manifest & Tapeout Release Management Own creation and governance of tapeout manifests including: PDK versions Tool versions Extraction/verification decks Simulation models Signoff configurations Establish reproducible environment release frameworks for analog programs. Implement controlled qualification flows for tool/PDK upgrades prior to production rollout. Maintain environment snapshots to ensure reproducibility and post-silicon traceability. Support formal tapeout readiness and design signoff reviews. Version Control & Configuration Management Deploy and manage version control systems (Git, SVN, Perforce) for: CAD scripts and automation Methodology flows PDK overlays Verification decks Define branching, tagging, and release strategies for multi-project and multi-node environments. Implement dependency tracking across tools, PDKs, IP, and infrastructure. Apply infrastructure-as-code principles where applicable. Automation & Traceability Develop automated environment capture tools to log tool versions, library states, and system configurations. Enable reproducible simulations and environment packaging. Create dashboards and reporting metrics for design data health and DA service KPIs. 4. Leadership & Cross-Functional Collaboration Lead and mentor DA and infrastructure engineers. Serve as the primary interface between analog design, digital CAD, IT, and EDA vendors. Drive tool evaluations, upgrades, and vendor negotiations. Develop internal documentation, training programs, and best practices. Establish measurable service-level KPIs and continuously improve DA operations. Required Skills and Experience Strong hands-on experience with analog design platforms such as Virtuoso and Custom Compiler. Deep understanding of analog layout, verification flows, PDK integration, and tapeout processes. Proven experience managing design data governance and tapeout manifest control. Strong Linux system administration and scripting skills (Python, Tcl, Shell). Experience with compute grid management, storage architecture, and license management. Expertise in version control and configuration management systems. Preferred Skills and Experience Experience with advanced nodes (FinFET, GAA). Familiarity with cloud-based EDA deployment models. Knowledge of CI/CD practices applied to EDA environments. Experience supporting geographically distributed design teams. Strong budgeting and vendor management experience. Key Competencies Technical depth in analog CAD methodologies Strong data governance and release discipline Strategic infrastructure planning Cross-functional leadership Process-driven execution with audit readiness mindset Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in analog/mixed-signal design or CAD support. 5+ years of leadership experience. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. The Role and Impact: Join Intel as a CPU Performance Architect in Austin, TX and play a pivotal role in advancing cutting-edge semiconductor technology. You will be at the forefront of designing and developing CPU logic, ensuring power, performance, and area optimization to meet Intel's world-class standards. As part of our innovative engineering team, your contributions will directly impact the success of Intel's CPU designs and their integration into system-on-chip (SoC) solutions. This is an exciting opportunity to shape the architecture and microarchitecture of CPUs, influencing the development of industry-leading processors that power the future of computing. Key Responsibilities: Develops and drives end-to-end CPU architecture specifications for highly optimized, modular, and scalable CPU based on hardware features, requirements, and interoperability of hardware and software throughout the product life cycle. Understands the CPU requirements and defines targets (performance, power, frequency, and area) and content (features) that meet the requirements. Evaluates feasibility trade-offs, explores, and defines new approaches and novel architectures for CPU. Invents, conceptualizes, and specifies architectural and microarchitecture features to deliver optimized CPU requirements for multiple segments from high performance computing to extreme low-power products. Models CPU performance and power, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage. Develops tests, test plans, and testing infrastructure for new architectures/features for CPU, performs functional modeling simulations, and conducts analysis of test results using advanced statistics and data predictions for benchmarking performance and determining areas for improvement. Provides experimental/proof-of-concept changes for proposing design alternatives meeting performance, power, area, and timing constraints. Collaborates with architects, design, verification, and validation engineers during the execution of the project. Delivers definition of new microarchitecture and finds mitigations for issues that arise during feature implementation to improve the overall design of CPU and overcome bottlenecks and constraints. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. Minimum Qualifications: The candidate must have a Bachelor's Degree in Computer Science, Electrical Engineering and Computer Science, Electronics and Communications Engineering or related computing discipline and 4+ years' related experience OR a Master's in Computer Science, Electrical Engineering and Computer Science, Electronics and Communications Engineering, or related computing discipline, and 3+ years related experience, OR PhD in Computer Science, Electrical Engineering and Computer Science, Electronics and Communications Engineering, or related computing discipline and experience listed below. High performance micro-architecture techniques and research CPU architecture and micro-architecture simulators, tracing technologies, and performance analysis. 6+ months experience or coursework with C++ Preferred Qualifications: PhD in Computer Science, Electrical Engineering and Computer Science, Electronics and Communications Engineering, or related discipline. Internship or experience in a CPU design or verification role. Advanced skills with Object Oriented Programming (C++/STL) Job Type: College Grad Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $141,910.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: The Role and Impact As a CPU Power Management Architect, you will be at the forefront of Intel's innovation, shaping the future of CPU designs for high-performance computing and low-power products. This role is integral to Intel's mission to deliver cutting-edge solutions that power the world's technology, from advanced data centers to everyday consumer devices. You will play a pivotal role in driving end-to-end CPU Power management architecture specifications, ensuring optimal performance, power efficiency, scalability, and interoperability across hardware and software. Through creative problem-solving and collaboration, you will influence cross-functional roadmaps, define technology targets, and deliver revolutionary CPU architectures that meet diverse market requirements. Key Responsibilities Define end-to-end CPU power management microarchitecture, including the design and specification of hardware mechanisms for dynamic voltage and frequency scaling (DVFS), power state transitions (C-states and P-states), thermal control, hotspot detection and mitigation, droop mitigation, ICCMAX enforcement, reset flow architecture, Machine learning algorithms for power and performance, power delivery and power gating techniques, as well as telemetry and debug capabilities. Explore new approaches and devise novel power management and thermal management solutions that deliver optimized CPUs for multiple segments, from high-performance computing to extreme low-power applications. Identify emerging market trends and translate them into novel features. Collaborate with RTL designers, SoC architects, and firmware/OS teams to ensure power management algorithms are implemented correctly and interface seamlessly with software. Review and influence cross-functional roadmaps and collaborate with architects, design, verification, and validation engineers during project execution. Participate in the post silicon debug and tuning of silicon. You will compare real-world power/performance data against your pre-silicon models to close the gap between theoretical projections and actual hardware results. Expertise in CPU architecture fundamentals, microarchitecture design, low-power design, RTL development, and System Verilog. Proven ability to debug microarchitecture and simulation issues and solve complex design problems. Strong understanding of system-level power and thermal constraints, and how they interact with user experience Ability to define and analyze power/performance KPIs and drive architectural decisions based on data. Extensive experience in low-power design, including RTL development and System Verilog. Experience with hardware/firmware/software co-design for complex power management systems. Qualifications: Minimum Qualifications BS in electrical and computer engineering 10+ years of experience working in CPU and SOC power management and thermal management architecture Preferred Qualifications Strong analytical and problem-solving skills demonstrated through leadership roles or team management. Effective collaboration skills to work across teams and influence cross-functional roadmaps. Passion for driving innovation and contributing to Intel's mission of delivering world-class technology solutions. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, Oregon, Hillsboro Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $190,610.00-361,480.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: For nearly a decade, Intel's Neuromorphic Computing Lab-together with a global ecosystem of 250+ research groups-has explored architectures, algorithms, and software inspired by the brain's extraordinary efficiency, scalability, and adaptability. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications that validate the promise of this novel approach. Now, we're entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems-beyond the reach of GPUs and mainstream AI accelerators. If you are passionate about pushing the boundaries of computing, from transistor-level innovation to software abstractions, join us. Help define the next wave of AI technology that harnesses the proven advantages of Intel's neuromorphic computing technology with the versatility demanded by modern AI workloads. Position Overview: Join the team building Intel's product-grade neuromorphic AI execution stack targeting edge and robotic systems. In this role, you will architect and lead the development of the firmware, runtime, and performance infrastructure, working closely with hardware, compiler, systems, and application teams to deliver a robust, observable, and high-performance software stack. You will set technical direction for a critical part of the platform while remaining hands-on in architecture and implementation. Responsibilities: Define and drive the technical vision, architecture, and roadmap for Intel's neuromorphic runtime software stack, while contributing hands-on to critical design and implementation. Architect, develop, and optimize firmware and runtime components, including execution control, scheduling, data movement, memory management, and device interfaces. Architect and deliver performance infrastructure, including profiling, tracing, debugging, benchmarking, and regression frameworks needed for optimization and product release. Integrate the runtime stack into existing robotics and edge software ecosystems, to enable efficient deployment and developer adoption. Collaborate with hardware, compiler, systems, application, and solution teams, as well as customers and external partners, to translate platform and workload requirements into robust software capabilities. Provide technical leadership across the runtime area by establishing engineering practices, driving software quality and release discipline, mentoring engineers, and helping scale the team over time. About the Organization: As part of Intel's CTO Office, you will join a vertically integrated incubation effort dedicated to bringing Intel's neuromorphic technology innovations to market. Our diverse team of engineers and researchers have pioneered sparse, event-based, neuromorphic architecture over multiple generations and is now focused on commercializing the technology in future Intel and partner products. Qualifications: Minimum Qualifications BSc, MSc, or PhD in Computer Science, Electrical/Computer Engineering, Physics, Mathematics, or a related technical field. 5+ years of experience developing firmware, runtime, performance, or other low-level systems software for AI or accelerators, including execution environments, profiling, debugging, and related infrastructure, with experience in technologies such as CUDA, LLVM, oneAPI, SYCL, ONNX, IREE, OpenVINO, TVM. 5+ years of experience leading software architecture for complex AI, runtime, or accelerator software systems, including defining technical direction and guiding implementation. 8+ years of experience developing maintainable, production-grade software in C/C++ and Python, including systems-level and performance-critical code, using disciplined engineering practices such as benchmarking, correctness and performance regression testing, build/toolchain management, and CI/CD. 5+ years of experience with AI, deep learning, or optimization workloads using frameworks such as PyTorch, JAX, or TensorFlow. Preferred Qualifications Experience managing and mentoring engineers, and leading delivery across cross-functional teams spanning hardware, systems software, compiler, and applications. Experience with robotics, edge, or real-time systems, including software ecosystems such as ROS2. Experience in HW/SW co-design, hardware simulator development, or software bring-up for emerging accelerator architectures. Experience with parallel computing paradigms or spatial / unconventional AI hardware accelerators. Experience with embedded or real-time Linux, device-driver / platform bring-up, or other low-level deployment software for edge systems. Prior contributions to open-source software projects. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, California, Santa Clara, US, Texas, Austin Business group: The mission of the Corporate Technology Office (CTO) is to incubate and develop strategically important emerging technologies that will serve as building blocks for computing systems and platforms of the future. This is done in collaboration with the business units of Intel, with the goal of transferring these technologies to the business units for productization and revenue generation. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $195,200.00-361,200.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: Intel’s AI SoC organization develops cutting-edge products powering a wide range of AI applications—from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, this is your chance to shape the future of AI hardware. Role Overview As a Lead Senior Design Engineer – AI SoC Development , you will be responsible for defining, implementing, and validating complex SoC IP blocks and subsystems, ensuring they meet stringent power, performance, and security requirements. You will collaborate across architecture, verification, and physical design teams to deliver high-quality silicon for next-generation AI solutions. Key Responsibilities Architectural Leadership: Evaluate trade-offs across features, performance targets, power constraints, and system limitations. Microarchitecture & RTL Development: Define and document microarchitecture for complex SoC IP blocks; implement RTL in Verilog/System Verilog, integrate at top level, and deliver synthesis- and timing-clean designs. Verification Collaboration: Partner with verification teams to ensure comprehensive coverage and robust validation of all design aspects. Timing & Physical Design Support: Develop and maintain timing constraints; guide physical design teams on synthesis, timing closure, and formal equivalence checks. Silicon Bring-Up: Drive post-silicon validation, debug, and performance analysis. Mentorship & Methodology: Mentor junior engineers and contribute to best practices for design methodology and quality. Additional Responsibilities Perform quality checks across RTL, timing, and power convergence. Apply secure development practices to address security threat models and objectives. Collaborate with IP providers for integration and validation at the SoC level. Drive compliance for smooth IP-to-SoC handoff. Additional Skills: Ability to lead projects, work cross-functionally, and deliver under tight schedules Strong communication skills and a collaborative mindset Qualifications: Minimum Qualifications Bachelor's or master's degree in electrical engineering, Computer Engineering, or Computer Science or related field with 10+ years of experience. 7+ years of experience in RTL design and implementation for ASIC/SoC development. Preferred Qualifications Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure. Hands-on experience with SoC system integration and multicore CPU subsystem design. Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures. Expertise in high-speed and low-power design techniques. Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization. Familiarity with industry-standard EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II). Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: US, California, Santa Clara, US, Texas, Austin Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: About the Role: The Sr. Director of Platform Planning & Program Management is responsible for managing the development timeline for all of Design Technology Platform (DTP) deliverables spanning PDKs, Foundational IPs, Reference Flows, and Platform Validation to meet release commits and customer needs. This leader is responsible for communicating risks, creating solution plans, and working closely with all domain owners to guarantee flawless execution. This leader serves as the delivery integrator and hence is responsible for working with all domain owners to plan the timeline of intermediate deliverables and to always foresee the status of development & interdependencies to always have a proactive plan to guarantee meeting delivery commit. Also, this leader will have a unique vintage point to identify improvement opportunities in both quality and efficiency. Experience Required: Semiconductor background to understand the impact of process feature add on PDK collaterals & FIP design PDK background to understand the interdependencies between different PDK components FIP background to understand the requirements of FIP design & expected deliverables Design Flow background to understand how PDK & FIP are utilized in design Program management skills to drive execution & discipline to deliver to commits Platform planning mindset to proactively collaborate with different area owners to deliver a complete & validated design platform. And identify efficiency improvement opportunities. The capability to foresee delivery risks, identifying work arounds for short term, and proposing long term improvements to avoid such risks in the future. Excellent customer services mindset and skills to guarantee meeting customer needs & timeline. Proven experience in building a high-performance team, developing leaders, and driving necessary organizational change and culture Able to build effective working relationships across all levels of the organization and influence the direction of the company. Innovative mindset to identify and drive improvement initiatives that target workflow efficiency, quality of deliverables, customer satisfaction, and AI solutions. Complex problem solving and decision-making skills with background in results orientation. Qualifications: Master’s or Ph.D. in Electrical Engineering or Computer Engineering 20+ years of industry and leadership experience including direct experience in design and design enablement Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $271,620.00-383,460.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in shaping the future of Intel's cutting-edge System on Chip (SoC) designs. This role offers an exciting opportunity to contribute to the development of world-class technology solutions that drive innovation across diverse industries. You will be responsible for developing high-quality logic designs, coding register transfer level (RTL) models, and performing thorough simulations to ensure optimal functionality. Your contributions will directly impact the success of Intel's products by enabling power-efficient, high-performance, and scalable solutions that meet or exceed market demands. Key Responsibilities Develop logic designs and RTL code for SoC designs, ensuring alignment with architectural and microarchitectural specifications Perform integration of logic for IP blocks and subsystems into full-chip SoC designs Conduct quality checks across various logic design aspects, including RTL, timing, power, and area convergence, and address design integrity for physical implementation Optimize logic designs to meet stringent power, performance, area, and timing goals Review verification plans and ensure the correctness of tested design features Resolve RTL test failures by implementing corrective measures to ensure design feature correctness Apply secure development practices to mitigate security threats and meet secure design objectives Collaborate with IP providers to integrate and validate IP at the SoC level Drive compliance with quality assurance standards to enable seamless IP/SoC handoffs Core Competencies Demonstrated ability to work collaboratively across teams and communicate effectively in complex technical environments Passion for innovation, problem-solving, and continuous learning within the field of SoC design Qualifications: The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related field 3+ years of experience in microarchitecture development, RTL coding, or logic design Experience in clock domain crossing techniques, low-power design methodologies, and SoC clocking structures Experience with tools and strategies for RTL design, SoC integration, and physical implementation optimization Preferred Qualifications Master's degree in Electrical Engineering, Computer Engineering, or in a STEM related field. Experience with secure development practices for secure design implementation. Experience in SoC Builder and Network-on-Chip (NoC) architectures. Become part of Intel's mission to advance technology and create products that enrich lives. Your expertise in SoC logic design can make a meaningful impact-join us today. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. The Physical Design Integration Engineer performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU. Optimizes CPU design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Responsibilities The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc Responsibilities may also include defining design requirements such as frequency, operating voltages, power, etc. to achieve optimized designs on new technologies, processes and architectures The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems Good leadership and communication skills are necessary due to the nature of the work, size and complexity of the products and the size of the team Qualifications: A successful candidate will have proven experience demonstrating the following skills and behavioral traits: Bachelor's in Electrical/Computer Engineering with 15+ years relevant work experience, or Master's in Electrical/Computer Engineering with 12+ years relevant work experience The ideal candidate will be capable of leading a small team as well as interacting with architecture and design teams to improve IP and ultimate product quality and performance Experience in: Logic Design, VLSI/ASIC Design, Computer Architecture Current Industry Experience in one or more ASIC style design flows - floorplanning, clock construction, synthesis, place and route, static timing analysis, layout verification Experience with Unix/Linux, Perl and TCL in order to implement useable, flexible cshell/perl/tcl programs that automate tool/flow methodologies Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: US, California, Santa Clara, US, Texas, Austin Business group: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $256,050.00-361,480.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. The Role and Impact: Intel's Consumer Industries vertical focuses on enabling intelligent, secure, and reliable transactional devices across the retail, grocery, hospitality, venues, and retail banking ecosystem. As workloads increasingly move closer to where data is generated and the industry is shifting toward edge native solutions that must operate within real-world constraints such as latency, data privacy, reliability, power, and regulatory compliance. In this dynamic position, you will also lead industry transformation with the design and development of integrated AI solutions that combine hardware, software, firmware, board, and silicon components, pushing technological boundaries to solve complex challenges that will transform vertical industries. The Consumer Industries vertical team operates at the intersection of technology, industry, and ecosystem partners to translate these constraints into actionable roadmaps and deployable solutions across point of sale, self-checkout, ATMs and edge-enabled transactional platforms. Success requires tight alignment between forward looking roadmap strategy, AI enablement, and practical solution definition, ensuring innovation at the edge can be validated, scaled, and adopted in real retail and service environments. We are seeking a Solution Lead to operate across portfolio roadmap ownership and customer and partner-facing solution definition. This role is intentionally balanced between shaping long term strategic direction and driving near-term solution clarity, ensuring strategic intent translates into executable, scalable growth and business outcomes. The ideal candidate brings hands-on experience, is comfortable navigating ambiguity, and can align product, engineering, and go-to-market stakeholders around clear priorities grounded in vertical industry needs. Key Responsibilities: Roadmap Planning and Portfolio Alignment • Own and drive roadmap requirements aligned to business objectives, device strategies, market needs, and technology readiness. • Translate industry trends, customer insights, regulatory considerations, and internal constraints into clear roadmap priorities and tradeoffs. • Partner closely with product management, engineering, and architecture teams to ensure feasibility, dependency management, and alignment with platform strategies. • Support annual and quarterly planning cycles by developing roadmap narratives, options, and scenario analyses for leadership decision making. • Identify portfolio gaps, overlaps, and risks, and proactively drives alignment and prioritization discussions across stakeholders. Solution Management and Engagement • Partner with device architects and technical leads to shape future state solutions and articulate the art of the possible for priority customers and use cases. • Act as a bridge between market requirements and internal execution, ensuring solutions are grounded in real-world deployment constraints. • Develop and align the business case by modeling revenue, margin, and growth scenarios for new segments, solutions, and GTM initiatives to inform investment and prioritization. • Partner cross-functionally with finance and business teams to validate assumptions, align forecasts, and track performance against growth targets. • Develop solution positioning, value propositions, and high-level capability definitions in collaboration with technical and business stakeholders. • Support priority customer, partner, and ecosystem engagements by clearly articulating solution direction, roadmap alignment, and differentiation. • Ensure learnings and feedback from customer engagements, pilots, and deployments are systematically fed back into roadmap Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Bachelor's degree in a related field such as Computer Science, Electrical Engineering, Systems Engineering or equivalent discipline; or a master's degree with 6+ years of experience; or an MBA with 6+ years of experience or equivalent experience 6+ years of experience in the retail industry developing checkout or transactional systems and solutions, or the retail ecosystem designing retail devices or solutions, including point of sale, self-checkout, or transactional systems. 4+ years of experience in product management, platform, or solution roadmap planning, or solution strategy. 2+ years of experience translating ambiguous market signals into structured priorities, roadmaps, and solution direction. This position is not eligible for Intel's immigration sponsorship. Preferred Qualifications: Strong communication and collaboration skills with the ability to work effectively across teams and disciplines. A passion for solving complex problems and driving technological advancements in AI, edge computing, or data-intensive workloads in consumer-facing industries or retail environments. Understanding of regulatory, privacy, and reliability considerations for transactional systems. Experience engaging directly with customers, partners, or ecosystem stakeholders in a technical or strategic role. Experience working cross-functionally with engineering, product, architecture, and go-to-market teams. Excellent executive-level communication skills, with the ability to align diverse stakeholders around complex tradeoffs. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Austin Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $195,200.00-361,200.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: Note: This role requires regular onsite presence to fulfill essential job responsibilities. Drives technology development and enablement for both high volume manufacturing and future technology, provides process integration and equipment solutions, and performs feasibility studies to meet desired device specifications. Leads design and development of technically sophisticated manufacturing processes and/or repair reverse engineering including material selection, parameter optimization, equipment metrology, and system design to enable new product designs and functional requirements. Performs pathfinding activities in support of process and hardware development enabling manufacturing of innovative device architectures and develops roadmaps for technologies enabling future roadmap. Recommends and implements modifications for operating equipment to improve production efficiency, manufacturing techniques, and optimizing production output for existing products. Partners with key equipment and materials suppliers to develop and implement enabling elements of the technology. Performs process technology feasibility studies through theoretical simulations and/or practical engineering methods. Remains updated on relevant industrial process and material manufacturing technical trends and develops view of inherent future Intel process technology needs to push industry forward by partnering with vendor ecosystem to build cost sensitive roadmap. Required Skills and Experience Proven track record of technical ownership and delivery of dry etch process innovations that enabled high volume manufacturing, yield improvement, reliability, or technology node transitions. Expert level understanding of plasma physics, plasma-surface interactions, pattern fidelity, selectivity, defectivity, and profile control for advanced device structures. Demonstrated ability to define long term technical direction and translate research concepts into manufacturable solutions at scale. Extensive experience with advanced data analytics, statistical modeling, and design of experiments (DOE) applied to complex semiconductor process problems. Recognized technical authority who influences decisions across modules, organizations, or technology programs without formal management authority. Preferred Skills and Experience Sustained leadership in developing and deploying next generation dry etch solutions for advanced logic or foundry technologies (e.g., FinFET, GAA, nanosheet architectures). Deep experience with advanced etch technologies, such as: High aspect ratio plasma etch (HARC); Atomic Layer Etch (ALE), EUV patterned layer etch integration; Radical and Vapor phase isotropic etching; Ash and surface treatments; Novel patterning or materials specific etch solutions Demonstrated history of breaking technical bottlenecks that materially impacted product ramp success, cost, or yield across multiple process nodes or product generations. Expertise in advanced materials and device characterization, including SEM, TEM, CD SEM, AFM, XPS, and electrical correlation. Strong publication, patent, or internal technology disclosure record that evidences field level or industry recognized contributions. Ability to mentor senior engineers, set technical standards, and elevate organizational capability across the dry etch discipline. Proven effectiveness in influencing cross functional and external stakeholders, including integration, device, yield, and equipment suppliers, to align on long term technical strategies. Experience shaping multiyear roadmaps for process platforms, tooling strategies, or foundational etch capabilities. Qualifications: PhD with 10+ years of directly relevant experience, or Master's degree with 15+ years of experience, in Chemical Engineering, Materials Science, Physics, Electrical Engineering, or a semiconductor related STEM field. Deep, authoritative expertise in dry etch semiconductor manufacturing, with demonstrated leadership over complex process development or platform level solutions. Experience working in dry etch in a foundry Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $211,400.00-298,440.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Life at Intel As a member of Intel's CPU development team, you will have a front seat in designing the latest core IP to power cutting edge compute processors across client, server, IOTG and AI. We innovate state of the art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency. Our core designs are present in nearly all segments of Intel's compute roadmap. Job responsibilities include but are not limited to: Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Bachelors in Computer Engineering or Electrical Engineering or related field with 2+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering or related field (or higher degree) with 1+ years of relevant work experience. 1+ years' experience in Synthesis of a digital logic block or partition. 1+ years of experience in each of the following: Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure. PV convergence (such as static timing and power analysis). Chip physical design verification including formal equivalence, electrical rules, DRC/LVS, and Noise flow. TCL Scripting. Preferred Qualifications: Knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution. At least 1 Completion of Tape Out on advanced technologies. Knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques. Knowledge of RTL to GDS methodologies and formal equivalence Experience performing CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements. Experience generating and verifying timing constraints while addressing timing violations at the chip or block level for CPU cores. Experience working closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. Benefits at Intel Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion. Job Type: College Grad Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $105,650.00-172,860.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Life at Intel As a member of Intel's CPU development team, you will have a front seat in designing the latest core IP to power cutting edge compute processors across client, server, IOTG and AI. We innovate state of the art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency. Our core designs are present in nearly all segments of Intel's compute roadmap. Job responsibilities include but are not limited to: Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, low power synthesizable CPU. Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Bachelors in Computer Engineering or Electrical Engineering or related field with 3+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering or related field (or higher degree) with 2+ years of relevant work experience. 2+ years' experience in Synthesis of a digital logic block or partition. 2+ years of experience in each of the following: Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure. PV convergence (such as static timing and power analysis). Chip physical design verification including formal equivalence, electrical rules, DRC/LVS, and Noise flow. TCL Scripting. Preferred Qualifications: Knowledge with Physical design best known practices concerning floor-planning, routing techniques, clock distribution. At least 1 Completion of Tape Out on advanced technologies. Knowledge of Static Timing Analysis, Noise analysis, and reliability verification techniques. Knowledge of RTL to GDS methodologies and formal equivalence Experience performing CPU level timing analysis and optimization, ensuring designs meet functional and performance requirements. Experience generating and verifying timing constraints while addressing timing violations at the chip or block level for CPU cores. Experience working closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning. Benefits at Intel Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: Join Intel's All Cores Engineering (ACE) Group as a Post Silicon Validation Engineer. Our team delivers Intel's industry leading P-Core IP solutions to our Xeon Server products for Data Center and Cloud customers. Intel Architecture (IA) Core Post Silicon Validation Engineers are responsible for core level validation of the leading CPU products of each new Intel P-Core product. To bring these features and new platforms to market, a Core Post-Si Validation Engineer needs to be an expert in CPU Post-Si debug and validation, have knowledge in test generators for core level validation, be involved in tasks such as developing validation plans, 'powering on' the very first system built with Intel's latest and greatest CPU, validating product features, and identifying and debugging all functional bugs. Our Engineers have great opportunities to enhance their skills in validation architecture and design. Various validation techniques are used, such as emulation, while offering a unique hardware-software experience. In addition to various tools, languages and validation methodologies, Engineers will develop expertise with Intel Architecture and Micro Architecture and will be deeply involved in the process of defining new Intel features. They are independent, creative, with the willingness to innovate new solutions and demonstrate uncompromised quality in their work. Good communication and interaction skills among groups is also important. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Bachelor’s degree in electrical/computer engineering or computer science and 6+ years of experience -OR- a master’s degree in electrical/computer engineering or computer science and 4+ years of experience -OR- a PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience in: C++ or Perl or Python CPU architecture / assembly Debug Preferred Qualifications MCA (Machine Check Architecture) RAS (Reliability Availability Serviceability) / SER (Soft Error Rate) Emulation Chip logical validation concepts and methodologies Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: The CPU Circuit Technology team is looking for a highly motivated and experienced individual to join our team as a Memory Circuit Design Engineer. In this role, you will be responsible for designing, developing, and building full-custom as well as compiler-based SRAMs, Large Signal Arrays (custom multi-ported register file), ROMs, custom memories, digital circuits and Caches for Intel CPUs and SOCs. You will be partnering with and leveraging domain experts across various areas of technology development to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on advanced CMOS process technologies for Intel CPU and SOCs. This will be a fast-paced dynamic environment where you will work in the high performance, low power CPU design team on a wide spectrum of circuit activities including, but may not be limited to: • Technical readiness, memory circuit design, characterization and simulations. • Cache design, critical path simulations and design custom blocks. • Memory path-finding activities and power, performance and area (PPA) optimization. • Memory bit-cell and complex periphery IC design and automation. • Memory array/IP design, memory circuit innovation. • Methodology definition tasks as well as executing to project schedules. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Qualifications: Bachelor's degree with 8+ years of experience; or master's degree with 6+ years of experience; or PhD with 4+ years of experience in in Electrical Engineering, Computer Engineering, Computer Science or a STEM-related field 3+ years of experience in CMOS circuit design, digital logic optimizations, and circuit trade-offs for power, performance, and area. 3+ years of expertise in SRAM and Cache design. Preferred Qualifications: Experience in low-power implementation techniques and memory design. Familiarity with circuit and layout trade-offs for optimized design. Knowledge of EBB design tools, flows and methodologies, and signal integrity analysis. Strong analytical and problem-solving skills, with the ability to prioritize tasks and work in dynamic environments. Help shape the future of technology and join a team that's driving innovation at the forefront of CPU design. Apply now to make a meaningful impact at Intel. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: The Role and Impact We are seeking a highly experienced a Director, SoC Design Engineering, to lead the functional verification efforts for cutting-edge system-on-chip (SoC) designs. In this strategic role, you will define and implement scalable and reusable verification methodologies that ensure first-pass silicon success. As a trusted domain expert, you will directly influence Intel's technical direction, mentor the next generation of engineers, and drive innovation that strengthens Intel's leadership in the semiconductor industry. This position offers a tremendous opportunity to shape the quality and performance of Intel products, ensuring they meet and exceed the expectations of customers worldwide. Key Responsibilities - Architect and define end-to-end SoC verification strategies, including simulation, emulation, and formal verification approaches, to validate complex SoC designs. - Develop and execute block, subsystem, and SoC-level verification plans, including test benches and coverage models, to ensure compliance with microarchitecture specifications. - Lead verification closure for critical interfaces, including AXI, ACE, CHI, and interconnect fabrics. - Collaborate with SoC architects, RTL designers, and firmware teams to define verification hooks, assertions, and coverage metrics. - Oversee the integration of multiple IPs such as PCIe Gen6/7, DDR5/6, and Ethernet into the SoC environment, driving verification success. - Define and promote reusable UVM-based verification methodologies and automation flows for improved team productivity. - Lead emulation and performance modeling efforts, including co-verification of digital designs with firmware and architectural simulations using advanced platforms like Palladium and Veloce. - Debug and root cause complex issues in pre-silicon environments, implementing corrective measures to ensure design functionality and performance. - Provide expert guidance and mentorship to technical leads and design verification engineers, fostering a culture of continuous learning and improvement. - Collaborate with post-silicon validation teams to incorporate learnings into future verification methodologies and infrastructure. Qualifications: Minimum Qualifications - Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field, with 12+ years of relevant experience; -5+ years of people management experience - Expertise in SystemVerilog and UVM/OVM verification methodologies. - Comprehensive knowledge of SoC microarchitecture, including coherency protocols, cache subsystems, and interconnect fabrics. - Proven experience with high-speed protocols such as PCIe, DDR, AXI, CHI, or NoC. - Hands-on experience with emulation and prototyping platforms (e.g., Palladium, Veloce, FPGA-based) and formal verification tools. - Demonstrated ability to develop and maintain verification environments, including scoreboards, monitors, and VIP integration. Preferred Qualifications Masters degree in Electrical Engineering, Computer Engineering +8 years work experience or PhD + 6 years in Electrical Engineering, Computer Engineering +6 years work experience - Familiarity with power intent verification (UPF) and security verification techniques. - Experience with AI/ML accelerators, custom interconnect fabrics, or SmartNIC technologies. - Strong scripting skills (Python, Perl, or TCL) to automate verification flows and regressions. - Proven ability to drive pre-silicon to post-silicon correlation for continuous improvement. - Exceptional analytical, debugging, and technical leadership abilities, with a passion for driving innovation and excellence. Join us and make a lasting impact on Intel's groundbreaking technologies and products. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Oregon, Hillsboro, US, Texas, Austin Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: As a Network Platform Architect, you will be at the forefront of defining, building, and securing Intel's network strategy, playing a pivotal role in creating the backbone that supports our cutting-edge technologies. This role is critical in driving architectural reviews, solving complex network challenges, and delivering secure and efficient infrastructure to meet the evolving needs of Intel's business. In this role you will define the platform integration and adapter architecture end-to-end for our networking products. The role will have significant collaboration with partners and customers to ensure you stay up to date with latest trends and technologies around connectivity, manageability, cooling, form factor etc. The role is critical in the definition of our next generation products. This role sits at the intersection of SoC architecture, board design, platform firmware/software, and OEM/ODM integration, ensuring that silicon capabilities translate into deployable, serviceable, and scalable adapter solutions. You will drive platform-level requirements and architecture closure early, aligning SoC capabilities with adapter constraints, customer/OEM expectations, and data center operational needs. Your expertise in network design, telemetry, monitoring and security will empower innovation across cloud technologies, analytics, AI, data centers, and more, ensuring that Intel remains a leader in the technology landscape. 1) IPU/DPU/NIC Card / Adapter Architecture Ownership Define the adapter card architecture for IPU-based NIC products, including form factor, I/O topology, feature partitioning (SoC vs board), and platform integration requirements. Own the board-level architecture: PCIe connectivity assumptions, retimer/redriver strategy, clocking/reset strategy, SPI/I2C/SMBus/USB topology, secure boot/update and debug hooks as they relate to the card. Drive system partitioning tradeoffs: what must live in SOC vs what can be implemented on-card (PHY topology options, management sideband bridging, sensors/FRU, etc.). Author and maintain platform architecture artifacts (adapter architecture spec, block diagrams, interface requirements, bring-up requirements, OEM integration guide). Lead cross-functional architecture reviews with silicon, board, FW/SW, validation, and manufacturing teams to ensure adapter design meets platform requirements. 2) Platform Manageability Interconnect and Serviceability Architecture Define the platform manageability architecture for the adapter across OEM variants, including: Sideband/manageability interface requirements and minimum viable feature set definition. Management traffic separation strategy (data-plane vs management-plane considerations) and platform integration constraints. Drive requirements and architectural decisions for manageability interconnect options (e.g., board-level vs SoC-level scope and ownership boundaries). Ensure the manageability solution supports operational needs: inventory, sensor/telemetry exposure, secure device identity, firmware lifecycle hooks, and platform compatibility constraints (including OEM differences). Coordinate with FW/SW teams to ensure manageability requirements are reflected consistently in requirements and translated into implementable roadmaps. 3) Platform Thermal, Power, and Reliability Requirements Own the adapter-level thermal and power envelope definition: Establish card power targets (typical/peak/transient), power states, and throttling/derating assumptions. Define cooling assumptions (airflow class, heatsink constraints, chassis limitations) and coordinate with mechanical/thermal engineering to close feasibility. Drive power delivery architecture requirements: VR selection strategy, rail budgeting, margin methodology, inrush/steady-state considerations, and platform constraints alignment. Define platform-level reliability and serviceability expectations: sensor placement/coverage expectations, fault containment, diagnostics/debug hooks, and service workflows. 4) Cross-Functional Leadership and Execution Serve as the single platform architecture voice connecting SoC architecture decisions with adapter constraints and OEM deployment realities (ensuring proactive alignment vs reactive late-cycle changes). Lead technical alignment across silicon architecture, board design, FW/SW, validation, and operations stakeholders to drive closure on platform-level risks. Partner with product/program leadership to define platform milestones, gating criteria, and review readiness for customer/OEM engagements. Qualifications: Minimum Qualifications 8+ years' experience in one or more of: NIC/adapter platform architecture, server platform architecture, SoC-to-board integration, or high-speed I/O platform design. Demonstrated experience defining adapter/card architectures that balance electrical, thermal, mechanical, cost, and manufacturability constraints. Strong understanding of platform manageability concepts and sideband integration constraints across OEM environments (requirements definition, MVP scoping, compatibility tradeoffs). Experience defining and closing thermal/power envelopes for add-in cards or tightly constrained platforms (including working with thermal/mechanical engineering and validation). Proven ability to drive cross-functional alignment and deliver architecture specifications that teams can execute against. Bachelor's degree in computer science, Network Engineering, or a related field, or equivalent experience in line with business needs. Preferred Qualifications Experience with hyperscale/OEM deployment constraints for adapter cards (serviceability, telemetry expectations, fleet operations patterns). Expertise in high-speed I/O and Ethernet NIC platforms (signal integrity tradeoffs, system bring-up realities, platform-level debug). Prior leadership owning platform readiness across multiple SKUs or OEM variants (balancing commonality vs forks). Familiarity with translating requirements into phased implementation plans under resource constraints. Strong problem-solving skills with a focus on delivering innovative and scalable solutions. Excellent communication skills to effectively collaborate with cross-functional teams and stakeholders. Proven ability to navigate complex business processes and translate them into actionable network strategies. Passion for staying abreast of emerging technologies and security trends. Embark on a career with Intel where you'll have the opportunity to shape the future of networking and security. Apply today to join a team that empowers innovation and delivers impactful solutions to the world's toughest challenges. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Arizona, Phoenix, US, Oregon, Hillsboro, US, Texas, Austin Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $203,200.00-286,870.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…

Job Details: Job Description: Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Life at Intel We developed the Intel E-Core microprocessors, a foundational technology that powers a diverse range of devices-from entry-level PCs to high-end gaming desktops and laptops, as well as data center solutions and many other applications. As part of our team, you will help design the next generation of high-performance microprocessors. We are looking for a skilled individual who has hands-on experience in RTL methodologies, coding, debug and effective use of AI tools and can provide technical leadership to deliver world-class products. As a Sr. CPU RTL Methodology Engineer your responsibilities will include but are not limited to: Demonstrated leadership and hands-on experience in leveraging AI tools and methodologies to drive significant efficiency gains and improvements in RTL coding and other areas of silicon development. Proactively advances front-end methodologies and contributes to architectural and microarchitectural discussions to enhance scalability and flexibility. Develops and implements strategies, tools, and techniques for RTL development and logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as physical design integrity. Possesses a comprehensive understanding of both front-end and back-end flows, with a proven track record of delivering solutions across multiple domains. Collaborates effectively with architecture, backend, and other design teams to deliver industry-leading products. Builds and sustains a high-performing, technically strong organization by fostering and upholding core group values, norms, and behaviors. Behavioral traits that we are looking for: Excellent in problem-solving, analytical skills. Excellent written and verbal communication skills Ability to work effectively in a fast-paced environment and collaborative environment Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Education Requirement: • Bachelor's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 12+ years of work experience OR • Master's degree in Computer Science, Electrical, Electronics, Engineering, or related field with 10+ years of work experience OR • PhD in Computer Science, Electrical, Electronics, Engineering, or related field with 6+ years of work experience Minimum Required Qualifications: • 6+ years of experience in silicon development of CPU logic. • 5+ years of experience in technical leadership and in delivering successful IP Projects Additional Preferred Qualifications: • Experience on x86 CPU microarchitecture • Experience with x86 memory management execution • Experience with driving front end methodologies and championing the use of AI tools to realize tangible benefits visible at the product level. Benefits at Intel Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, Arizona, Phoenix, US, Oregon, Hillsboro Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Intel

Intel's innovation in cloud computing, data center, Internet of Things, and PC solutions is powering the smart and connected digital…