Astera Labs

You'll develop and execute electrical validation tests for **DDR memory** on AI connectivity products, ensuring **parametric conformance** to customer requirements. You'll own post-silicon validation plans and automate testing for complex SoCs.

You'll lead **product engineering** for **next-gen high-speed connectivity** solutions enabling **rack-scale AI infrastructure**. Your team will drive silicon from bring-up through high-volume manufacturing, shaping the future of AI.

You'll develop production-grade diagnostics and manufacturing software for cutting-edge data center connectivity products. Collaborating with hardware engineers, you'll bring up new boards, validate ASICs, and drive test automation from concept to mass production. This role offers broad impact across design, validation, and manufacturing at a leading AI infrastructure company.

You'll lead global **AI hardware design programs** for rack-scale systems at a **NASAQ-listed connectivity innovator**, collaborating with hyperscalers and Tier-1 customers to deliver next-generation infrastructure like **UALink switch trays**. Your work will directly enable the future of AI computing.

You'll lead **emulation environments** to stress test **complex ASICs** for AI infrastructure at Astera Labs. Your work ensures reliable **PCIe, Ethernet, and DDR protocol** verification.

You'll define the electrical architecture of our next-generation **active copper cable assemblies** and pluggable modules for **400G/800G+ data center AI networks**. As the primary hardware authority you'll drive design from concept to production, influencing cross-functional teams and hyperscale customers. **This role offers strategic technical ownership** in a rapidly scaling AI infrastructure company.

You'll own full-chip **static timing analysis (STA) signoff** for Astera Labs' next-gen AI connectivity silicon. Your work directly enables **PCIe, CXL, UALink, and Ethernet platforms** that hyperscalers depend on. This is a high-impact leadership role at a hyper-growth company purpose-built for AI infrastructure.

You'll design and optimize power delivery systems for **ASIC products** at **Astera Labs**, a leader in AI infrastructure. Your work will ensure stable performance and robust power integrity for cutting-edge rack-scale connectivity solutions. You'll collaborate with cross-functional teams and vendors to deliver high-performance board-level designs.

You'll drive **timing closure** for **AI connectivity ASICs** used by leading cloud providers. Your work directly enables robust full-chip timing for **complex SoCs at advanced nodes**. This role offers end-to-end ownership of STA from RTL through sign-off.

You'll **root-cause complex failures** in high-speed connectivity products for **AI infrastructure**. Collaborate with design and systems teams to resolve issues at the circuit, firmware, and protocol level. Stand out by working with cutting-edge PCIe Gen6 and retimer technologies.

You'll define and execute **post-silicon validation plans** for Astera Labs' industry-leading **AI connectivity solutions**. Your work will directly certify product parametric compliance and ensure robust, production-ready designs for hyperscale customers.

You'll lead the **product roadmap** for a unified management suite that sits at the critical interface between host software, firmware, and silicon across Astera Labs' connectivity portfolio. Your work will enable hyperscalers and enterprises to configure and orchestrate **AI server platforms** at scale. This role offers a unique opportunity to define how **software communicates with chips** in the industry's most advanced connectivity solutions.

You'll define go-to-market strategy for Astera Labs' **Leo Smart Memory Extender**, a CXL-based solution for AI infrastructure. You'll shape **market narratives** that influence hyperscaler architecture decisions and drive **thought leadership** in memory disaggregation. This is a rare opportunity at a hyper-growth public semiconductor company building the connectivity backbone of AI.

You'll develop and support **physical design CAD flows** for chips powering the world's largest AI clusters. Your work will ensure **high-precision parasitic extraction** and drive **automation and GenAI integration**. This role offers meaningful technical ownership in a new R&D center.

You'll develop and perform system validation tests for AI connectivity solutions using leading-edge data center equipment. Your work certifies product conformance to customer requirements and automates validation for **high-speed protocols** and **scalable platforms**.

You'll lead **design verification** for **high-speed SerDes products** in a **cutting-edge AI infrastructure** company, collaborating with RTL designers to debug and ensure chip quality.

You'll validate optical systems for **AI connectivity solutions** at a **NASDAQ-listed company** collaborating with hyperscalers. Your work will directly impact **end-to-end production readiness** from concept to mass production.

You'll formulate and execute post-silicon validation plans for **AI connectivity products**, driving parametric performance and margin quantification. Your core impact is certifying product conformance to **hyperscaler requirements** using automated testing and data analysis.

You'll lead **advanced-node ASIC development** from concept through production for **AI infrastructure solutions** at Astera Labs. You'll own end-to-end program execution, driving cross-functional teams to deliver **revenue-critical silicon** on time and at scale. This high-visibility role directly impacts the company's core products.

You'll drive micro-architecture and RTL implementation for next-gen **AI infrastructure connectivity** chips using protocols like PCIe Gen 6/7 and CXL. Your work will directly impact the performance and power of **hyperscaler data center systems**. This role offers a chance to shape design methodologies and mentor teams at a **Nasdaq-listed AI connectivity leader**.

You'll lead **end-to-end validation and characterization** of advanced photonic integrated circuits (PICs) integrated with electronic ICs for **next-gen optical engines** in AI/ML data centers. You'll shape test strategies and drive reliability qualification.

You'll architect and develop bare-metal firmware for Astera Labs' next-generation connectivity products. **Embedded firmware** is a core differentiator, and you'll lead bring-up, debug, and validation on silicon. You'll collaborate closely with RTL and architecture teams to define HW-SW interfaces.

You'll **own core HR operational processes** and **build people analytics dashboards** to drive data-driven decisions. You'll enable scalable, AI-enhanced HR operations during rapid growth at Astera Labs.

You'll join Astera Labs' HR Programs team to design, execute, and improve talent management initiatives. You'll own real deliverables on projects like onboarding revamps and early career programs. This is a **hands-on internship** at a **fast-growing AI infrastructure company**.

You'll lead the DFT team developing next-generation connectivity products for AI infrastructure. Your work ensures full product lifecycle success from definition to mass production. You'll collaborate cross-functionally with engineering teams on **test generation** and **yield learning**.

You'll join a new R&D center in Israel, building verification environments for AI connectivity chips. You'll own unit- and subsystem-level functional verification of complex digital designs, driving designs toward **100% verification closure**. This role offers **meaningful ownership** and the chance to shape a greenfield site.

You'll **establish and lead Astera Labs' Shanghai hardware design center**, driving **AEC/SCM product design** from architecture through production. You'll serve as the **front-line hardware engineering partner for China-based customers**, supporting hyperscale AI infrastructure deployment. This role combines product ownership with regional customer impact.

You'll establish and lead Astera Labs' **Taiwan hardware engineering center** as the primary hub for OEM customer engagement across Asia. You'll own the design and development of **Silicon Validation Platforms** and **rack-scale products** for AI infrastructure. This high-impact role combines OEM design enablement, platform design, and system-level hardware leadership.

You'll lead and scale the **hardware design engineering organization** for **Active Electrical Cables and Smart Cable Modules** at a key AI infrastructure company. Your teams will own the complete hardware realization of connectivity products and enable OEM customers to integrate Astera Labs silicon. This role offers **high impact in a hyper-growth environment**.

You'll lead **end-to-end product integration** for Active Electrical Cables, ensuring all domains from silicon to signal integrity converge into a validated, production-ready product. You'll be the **single technical point of accountability** for cross-domain integration, driving resolution of the toughest challenges. This role offers deep technical influence without large-team management.

You'll lead **cross-functional engineering teams** to develop high-speed electrical interconnect products like **active electrical cables and smart cable modules**. Your work will drive **technology roadmapping and execution** from concept through launch, enabling rack-scale AI infrastructure for hyperscalers.

You'll lead firmware quality assurance for **PCIe switch products** at Astera Labs, a leader in AI infrastructure connectivity. Your work will directly impact **performance validation** for hyperscaler and Tier 1 OEM deployments.

You'll lead the entire production department at Astera Labs, overseeing all production processes and managing the team to ensure safe, on-time, quality- and cost-efficient series production. Your core impact is driving continuous improvement through lean management and CIP methods while maintaining high standards in a high-precision semiconductor environment. This role stands out for its combination of strategic leadership and hands-on involvement in a cutting-edge AI infrastructure company.

You'll lead the development of an **AI-powered IP Lifecycle Management and Quality Assurance platform** for a **NASDAQ-listed AI infrastructure company**. Your core impact will be ensuring **seamless SOC readiness** of all IPs, preventing late-stage tape-out delays. This role offers the opportunity to architect an AI-first ecosystem from the ground up.

You'll drive **data center memory solution architecture** and define future products for Astera Labs' **Intelligent Connectivity Platform**. Your core impact is solving **customer bottlenecks in hyperscale data centers** through hardware-software co-design and direct customer engagement.

You'll lead **advanced node BiCMOS/CMOS chip top-level layout integration** and block-level design for **high-speed analog mixed-signal ICs** at Astera Labs, driving **AI infrastructure connectivity solutions**. You'll collaborate cross-functionally to ensure robust tapeouts with strict DRC/LVS compliance.

You'll lead **PCIe switch validation** for **AI infrastructure connectivity solutions** at Astera Labs. You'll design and execute functional and stress tests to ensure product quality. This role offers impact on cutting-edge data center technologies.

You'll own **Smart Cable Modules** portfolio for **AI data center connectivity**, working with hyperscalers. You'll translate customer requirements into differentiated products and guide development from concept to launch. This is a high-visibility role shaping the future of AI infrastructure.

You'll join the DSP SerDes team at **Astera Labs** to develop **advanced high-speed SerDes transceivers** for AI systems. Your work will directly enable **rack-scale AI infrastructure** through purpose-built connectivity solutions.

You'll lead **thermal/mechanical modeling strategies** for **advanced IC packages** enabling next-generation AI and high-performance connectivity systems. Your core impact is driving chip-package-board co-design and first-pass production success. You'll directly engage with customers and influence package architecture decisions.

You'll support design-in of **connectivity products** for cloud service providers and OEMs, providing technical guidance to overcome design challenges. You'll investigate and resolve customer issues, and drive innovation through **feedback to internal teams**. This role combines direct customer support with deep lab work on **leading-edge semiconductor solutions**.

You'll lead pricing strategy for **AI infrastructure products** at a **NASDAQ-listed semiconductor company**. Your work directly shapes **revenue and margin outcomes** through data-driven decisions. This role offers high visibility with executive stakeholders and influence across product lines.

You'll own and develop formal verification environments for chips powering the world's largest AI clusters at a **foundational R&D center in Israel**. You'll define the formal verification strategy, proving **correctness of complex designs** and collaborating with architecture, design, and DV teams. This role offers **meaningful product ownership** in a new site from the ground up.

You'll lead **manufacturing projects** for Astera Labs' AEC/AOC connectivity ASICs used by top cloud providers, overseeing production from NPI to mass production. Your core impact will be ensuring **on-time, within-budget delivery** while coordinating cross-functional teams. This role offers **30% travel** and the chance to work with cutting-edge AI infrastructure technology.

You'll architect and implement **high-performance network controllers** for **AI infrastructure solutions** at a leading connectivity company. Your core impact is driving complex designs from micro-architecture to GDS. You'll work on **cutting-edge protocols** and collaborate with hyperscalers.

You'll lead **strategic ecosystem partnerships** with CPU, GPU, and XPU platform providers to drive adoption of **Astera Labs' Intelligent Connectivity Platform** in Asia. Your core impact is defining product positioning and enabling cross-functional teams to deliver **rack-scale AI infrastructure solutions** for hyperscalers. This high-visibility role reports directly to executive leadership and requires deep AI and cloud infrastructure expertise.

You'll provide technical guidance to ODMs and drive innovation for **PCIe/CXL semiconductor products** at a rack-scale AI infrastructure company. You'll own issue resolution from lab debug to customer communication, shaping next-gen connectivity solutions.

You'll execute **SI planning, design, modeling, simulation, and lab validation** for AI connectivity products. Your work ensures **high-speed signal integrity across complex system configurations**. You'll collaborate cross-functionally to **define hardware constraints and technology roadmaps**.

You'll own and scale **Salesforce platform management** and **business workflow automation** for a fast-growing AI infrastructure company. You'll drive system integrations, optimize approval processes, and partner cross-functionally to improve operational efficiency. This role offers high ownership and visibility across the organization.

You'll lead **system architecture** for next-generation AI compute platforms at Astera Labs. You'll drive **PCIe subsystem design** and **GPU integration** that powers hyperscale AI infrastructure. This role owns end-to-end platform delivery from concept to validation.

You'll join a **new Israel R&D center** building verification environments for **next-generation AI silicon**. You'll own unit-level and subsystem functional verification for **high-performance digital designs** that power the world's largest AI clusters.

You'll architect and optimize chip-package-board SIPI solutions for Astera Labs' **next-generation connectivity products** supporting PCIe, CXL, and high-speed SerDes. Your work will directly **enable scalable AI infrastructure** through advanced packaging platforms like 2.5D/3D integration and chiplet-based designs. This role offers leadership in **cross-functional execution** with top hyperscalers and ecosystem partners.

You'll serve as the primary technical resource for customers deploying **Taurus Ethernet Smart Cable Modules**, driving **system-level debug and validation** of high-speed interconnects. Your insights will directly influence product evolution at a hyper-growth company defining **AI infrastructure connectivity**.

You'll lead **end-to-end system architecture** for next-generation x86 and accelerator-based server platforms, defining **multi-platform design standards** that scale across product lines. Your work directly impacts how AI infrastructure is deployed at the rack and cluster level, collaborating with hyperscalers and silicon vendors.

You'll lead **development of advanced photonic packaging solutions** for next-gen AI infrastructure at Astera Labs, driving **Silicon Photonics Module packaging from concept to high-volume manufacturing**. Your work will directly enable **rack-scale connectivity for hyperscale data centers**.

You'll join a key team designing sophisticated advanced node CMOS products for **AI infrastructure connectivity solutions**. Your work will directly impact the performance of high-speed analog and mixed-signal circuits in **cutting-edge semiconductor technologies**. Collaborate with global teams to deliver tailored architectures for hyperscalers.

You'll own product definition and planning for Astera Labs' Taurus Ethernet Retimer portfolio, driving products from ideation to launch. Your core impact will be translating **hyperscaler customer needs** into competitive silicon and software solutions. This role offers direct collaboration with **AI infrastructure leaders** and ample growth opportunities.

You'll lead the definition and development of **next-generation DSP architectures** for **high-speed PAM4 optical transceivers**, driving the roadmap for 800G, 1.6T, and beyond. Your work will bridge theoretical communications theory with silicon implementation, impacting **AI infrastructure connectivity**.

You'll lead **post-silicon validation** for **mixed-signal connectivity solutions** at Astera Labs, a company building AI infrastructure. Your core impact will be driving end-to-end characterization and debug of high-speed silicon, ensuring performance and reliability before production. This role stands out for its influence on cutting-edge **AI rack-scale systems**.

You'll **architect and implement** next-generation digital designs for **high-performance connectivity solutions** at a company powering AI infrastructure. You'll own complex blocks from micro-architecture through silicon bring-up, collaborating with cross-functional teams to deliver production-ready designs.

You'll be the **technical authority for quality** across Astera Labs' optical product line and **regional quality lead for European operations**. Your core impact is bridging HQ (San Jose) with the Aachen manufacturing site to drive quality integration. This role stands out for combining semiconductor and photonics quality leadership in a high-growth AI infrastructure company.

You'll **develop and optimize embedded firmware** for optical engines and photonic integrated circuits at Astera Labs, a leader in AI infrastructure connectivity. Your work directly enables **high-speed 400G/800G/1.6T+ optical links** for hyperscale data centers. This role sits at the intersection of **photonics, embedded systems, and hardware integration**.

You'll define the end-to-end architecture for **next-generation AI infrastructure** platforms, spanning server firmware, high-speed connectivity, and rack-scale system design. You'll drive innovation across silicon integration and platform firmware to enable **hyperscale AI training and inference workloads**. This high-impact role offers the opportunity to shape the **connectivity backbone of modern data centers**.

You'll **architect and implement next-generation digital designs** for high-performance AI connectivity solutions at Astera Labs. You'll **own complex blocks from micro-architecture through silicon bring-up**, driving RTL implementation and collaborating with verification, physical design, and DFT teams. This role offers the opportunity to work on cutting-edge technology **at the forefront of AI infrastructure**, directly impacting products deployed by the world's leading hyperscalers.

You'll join the Hardware Electrical Validation team at Astera Labs, linking hardware design and post-silicon teams. You'll **develop validation plans** and **debug complex hardware failures** on PCBs. This role is key to **de-risking new designs** for AI connectivity solutions.

You'll lead **supplier quality management** for Astera Labs' semiconductor and board-level products, driving predictive quality through **advanced data analytics** and AI/ML. Collaborating with cross-functional teams, you'll ensure robust supplier selection and continuous improvement across global manufacturing partners.

You'll lead **ATE test solutions** for **complex mixed-signal SoC products** at Astera Labs, a leader in AI infrastructure. Your work directly impacts **high-volume production ramp** and product quality. You'll collaborate with top engineers and use cutting-edge protocols like PCIe Gen 5/6.

You'll serve as a **critical technical bridge** between customers and engineering for **Aries PCIe Retimer products**, powering AI data centers. You'll drive adoption with hyperscalers and OEMs while **solving complex system-level challenges**. This role offers exceptional visibility and impact in shaping next-gen AI infrastructure.

You'll join a key team designing **advanced node CMOS products** for AI connectivity solutions at Astera Labs. Your core impact will be developing and verifying circuits like PLL, DLL, ADC, and CDRs to meet performance targets. This role offers the chance to work on **purpose-built connectivity** for hyperscaler AI infrastructure.

You'll **lead functional verification** of advanced ASICs at a company powering **rack-scale AI infrastructure**. Your work will directly impact cutting-edge SoC designs for hyperscalers and ecosystem partners.

You'll support **cloud service providers** and server/network OEMs in designing solutions using our connectivity products. You'll identify customer needs, propose tailored solutions, and provide hands-on design-in support. This role stands out for driving innovation by translating customer requirements into product roadmaps.

You'll lead **firmware-focused customer engagements** for Leo CXL Smart Memory Controllers at **hyperscaler and OEM customers**, owning bring-up, validation, and issue resolution. You'll drive **firmware solutions** from early silicon through production ramp, translating requirements from CXL and JEDEC specs into robust implementations.

You'll develop and perform system validation tests for **AI connectivity solutions** using leading-edge Data Center equipment. Your work certifies product conformance to **customer system requirements**, directly impacting AI/ML infrastructure. You'll collaborate with **hyperscaler customers** to highlight Astera Labs' unique capabilities.

You'll develop **embedded firmware** for Ethernet retimers and gearboxes powering **AI infrastructure** in data centers. Your work directly impacts the performance and reliability of high-speed connectivity solutions. You'll take ownership of feature development, customer integration, and debug activities in a fast-moving startup environment.

You'll join a founding engineering team at Astera Labs' new R&D center in Israel, learning physical design for cutting-edge AI chips. Working under senior mentors, you'll support implementation and signoff tasks. This internship offers hands-on experience with advanced semiconductor processes for the world's largest AI clusters.

You'll support foundry engagement, silicon-to-model correlation, tapeout readiness, and yield improvement for **advanced semiconductor products**. You'll work with internal teams and foundry partners to resolve process, PDK, and silicon issues. This role offers the chance to impact **AI infrastructure connectivity solutions** at a **fast-growing public company**.

You'll lead manufacturing strategy and execution for **Smart Cable Modules**, **AI Chassis-class systems**, and **ODM-built products** at a fast-growing AI infrastructure company. Your core impact will be driving quality, capacity, and time-to-market across contract manufacturers in Asia. This role offers the opportunity to shape the hardware operations of a company powering rack-scale AI.

You'll lead the **optical test engineering** team for **next-generation AI interconnect solutions**, defining test strategies for integrated optical-electrical modules. Your work will directly impact the validation and manufacturing of cutting-edge data center infrastructure.

You'll support the finance team in an **international environment**, handling **invoice processing**, **OPEX planning**, and **ERP migration**. This part-time internship offers hands-on experience in accounting and financial analysis at a Nasdaq-listed AI infrastructure company.

You'll bridge firmware development and system validation teams to **debug Ethernet retimer firmware** on AI infrastructure. Your core impact is triaging and fixing real link failures in the lab and field, **unblocking customer deployments** without long handoff loops. This role stands out because you'll own both debug and **new feature development** for cutting-edge connectivity solutions.

You'll lead **sourcing and procurement** for capital equipment, IT hardware, and corporate services at Astera Labs, a company building **AI infrastructure connectivity solutions**. You'll drive supplier selection, negotiations, and cost savings while collaborating with engineering and IT teams. This **six-month contract** offers hands-on impact in a high-growth environment.

You'll join Astera Labs' Talent Acquisition team to identify and attract top-tier talent for a hyper-growth AI infrastructure company. You'll partner with hiring managers to execute full-cycle recruiting for engineering, operations, and corporate functions. This role offers the chance to build teams shaping the future of data center connectivity during the **AI revolution**.

You'll lead **sourcing initiatives** across components, PCB, PCBA, and mechanical parts for a **fast-growing AI infrastructure company**. Your core impact will be aligning sourcing strategies with technology roadmaps to drive cost optimization and supplier performance. This role offers a unique chance to influence the sourcing strategy behind cutting-edge products.

You'll analyze large-scale semiconductor test data to optimize processes and improve quality. Your core impact is developing **predictive models** for yield and failure analysis. This role offers the chance to bridge **test engineering and data science** at a leading AI infrastructure company.

You'll assist in developing **micro-architecture and RTL** for complex digital blocks that power AI infrastructure. You'll gain hands-on experience with **industry-standard EDA tools** and collaborate with cross-functional teams. This internship offers a unique chance to contribute to cutting-edge connectivity solutions at a fast-growing company.

You'll assist in building and maintaining **SystemVerilog/UVM-based testbenches** for high-performance digital blocks. This role offers **hands-on experience with advanced verification methodologies** and the chance to contribute to chips powering AI infrastructure. Work alongside world-class engineers to ensure chips are bug-free and robust.

You'll lead the **DFT architecture** for complex SoCs enabling **AI infrastructure at scale**, shaping our new Israel R&D center from the ground up. Your work will directly impact **first-pass silicon success** and production quality for next-gen connectivity solutions.

You'll own the DFT architecture and strategy for **AI connectivity chips** that power the world's largest AI clusters. Your work ensures flawless testability and reliability from RTL to production. This is a foundational role building a **new R&D center** in Israel.

You'll join Astera Labs' new Israel R&D center as a core contributor ensuring **power robustness** and **reliability of AI connectivity chips** in advanced FinFET nodes. You'll own IR drop and EM analysis, partner with physical design and package teams, and use tools like **Ansys RedHawk-SC** and **Cadence Voltus** to deliver **high-performance silicon for hyperscale AI clusters**.

You'll join a new R&D center driving **semiconductor connectivity solutions** for AI infrastructure. Your core impact is ensuring power robustness and reliability of chips powering **the world's largest AI clusters**. This role offers early-stage technical ownership in a growing Israeli site.

You'll define **next-generation architectures** for high-speed connectivity solutions that power **AI infrastructure**. You'll collaborate with hyperscalers to enable scalable, low-latency systems. This role offers a unique opportunity to **shape technical direction** at a new Israel site.

You'll design and develop **advanced node CMOS layouts** for high-speed analog ICs, collaborating with a global team to deliver connectivity solutions powering modern AI infrastructure. The role involves floor planning, parasitic minimization, and integrating building blocks like PLL and ADC.

You'll define product requirements and prioritize features for the **Scorpio Smart Fabric Switch portfolio**. Your work will directly impact **cloud and AI infrastructure customers** by translating their needs into competitive silicon and software solutions. This role offers **high visibility to executives and customers** in a fast-growing company.

You'll lead **high-speed semiconductor product development** for **AI infrastructure solutions** at Astera Labs. Your core impact will be driving new products from design to manufacturing, ensuring quality and performance. You'll collaborate with cross-functional teams in a **fast-paced, mission-critical environment**.

You'll **drive product quality improvements** across semiconductor and board-level products at **Astera Labs**, a leader in AI infrastructure connectivity. You'll perform failure analysis for customer returns, compile 8D reports, and communicate findings to customers.

You'll join the CTO Organization at Astera Labs, a leader in rack-scale AI infrastructure. Your core impact is ensuring efficient production planning and material availability for on-time manufacturing. This role stands out for its focus on **optimizing production processes** within a **cutting-edge AI company**.

You'll lead **optical test strategy development** for **co-packaged optics (CPO) solutions** in a high-impact **senior technical leadership role**. You'll architect test methodologies and hardware/software platforms to enable high-volume manufacturing of next-gen AI infrastructure.

You'll lead **design verification** for **AI infrastructure connectivity solutions** at Astera Labs. Your core impact is ensuring bug-free silicon for hyperscale data centers using **UVM and C/C++ environments**.

You'll design **high-performance digital solutions** for **rack-scale AI infrastructure** at Astera Labs. Your **block-level and full-chip designs** will drive cutting-edge connectivity at nodes ≤16nm.

You'll join a founding engineering team at a **NASDAQ-listed AI infrastructure company** to develop software for next-gen hardware platforms. You'll learn from senior engineers while building **test frameworks, automation tools, and low-level systems**. This role bridges academic studies with high-impact work in cutting-edge **semiconductor and AI technologies**.

You'll join a new R&D center in Israel to design digital blocks for AI connectivity solutions. You'll own **RTL implementation** from micro-architecture to backend support, tackling complex logic challenges for **AI infrastructure chips**. This role offers early ownership and impact on cutting-edge semiconductor technology.

You'll join the founding backend team establishing a new R&D center in Israel, owning the full physical implementation journey for chips powering AI clusters. You'll drive **block-level floorplanning** and **timing signoff** to ensure first-pass silicon success. This role offers **meaningful product ownership** in a cutting-edge semiconductor environment.

You'll join a new R&D center in Israel to build and optimize the backend execution environment for chips powering AI clusters. You'll develop automated flows from RTL to GDSII, enabling the PD team to deliver high-performance designs. This role offers meaningful technical ownership with direct EDA vendor collaboration.

You'll join Astera Labs' team to verify **complex SoC/silicon products** for AI infrastructure. Your work ensures **robust connectivity solutions** for hyperscalers. The role offers exposure to cutting-edge **CXL®, Ethernet, and PCIe technologies**.

You'll serve as the **technical bridge** between customers and engineering teams, supporting **PCIe retimer, Ethernet fabric switch, and CXL memory platforms**. You'll help hyperscaler and OEM partners design and deploy silicon into **AI infrastructure systems** reshaping data center landscapes.

You'll build **production AI systems** for technical users at a company enabling rack-scale infrastructure. Your core impact includes designing agentic workflows and evaluation loops that turn **modern model capabilities** into reliable tools used daily. You'll iterate directly on retrieval quality, tool interfaces, and deployment.

You'll assist with **customer engagements** for Leo CXL Smart Memory Controllers, including bring-up support and issue triage. You'll develop and debug firmware using **C and Python** across PCIe/CXL and DDR subsystems. This role offers hands-on lab work and direct customer interaction at a leading AI infrastructure company.

You'll build the runtime, platform, and operational backbone for modern AI systems at Astera Labs. You'll work on **model gateways, routing, telemetry** and **observability** to make fast-moving AI reliable. This role directly impacts how applied AI teams can move fast without losing quality or trust.

You'll lead **go-to-market strategy** for Astera Labs' PCIe signal conditioning products, shaping how hyperscalers adopt **AI infrastructure connectivity solutions**. You'll drive positioning, messaging, and competitive strategy while partnering with engineering and executive leadership.

You'll lead **functional verification** of complex ASICs at Astera Labs, a leader in AI infrastructure connectivity. You'll own the full verification lifecycle from planning to coverage closure, working with software and system validation teams on **emulation platforms**.

You'll lead a team delivering micro-architecture and front-end digital design for high-speed connectivity solutions at Astera Labs, a company building rack-scale AI infrastructure. Your core impact will be optimizing SerDes DSP design for power and area efficiency in next-generation ASICs. This role offers the chance to work with **cutting-edge CXL/PCIe and Ethernet protocols** in a fast-growing **NASDAQ-listed company**.

You'll develop **ASIC verification environments** for **AI infrastructure connectivity solutions**. You'll own functional coverage closure and collaborate with design engineers to resolve complex bugs. This is a ground-floor opportunity at a **new Israel R&D center**.

You'll lead **ASIC development** for **AI infrastructure chips** at a new R&D center, driving complex semiconductor projects from concept to production. Your core impact will be establishing technical standards and execution culture while managing cross-functional teams to deliver high-performance silicon.

You'll build and scale the system validation organization for **Astera Labs' connectivity products** used in AI data centers. You'll own comprehensive validation plans, drive test automation, and engage directly with **hyperscaler customers** to ensure performance and reliability. This role is critical for enabling next-generation AI infrastructure.

You'll execute end-to-end emulation flows for **AI infrastructure connectivity chips** at Astera Labs' new Israel R&D center. Your work will **validate cutting-edge silicon** that powers the world's largest AI clusters. You'll bridge **hardware-software integration** using industry-standard emulators.

You'll lead the **AI Fabric Validation organization** for a **NASDAQ-listed AI infrastructure company**. Your team will ensure **connectivity solutions perform at scale** for hyperscale data centers, shaping validation strategy for cutting-edge silicon.

You'll join a new R&D center in Israel to **develop parasitic extraction methodologies** for cutting-edge AI chips. You'll own the accuracy of extraction environments enabling **high-speed designs from RTL to GDSII**. This role offers meaningful technical ownership in a strategic new site.

You'll formulate post-silicon validation plans and automate testing for **AI connectivity products** at a leading infrastructure company. Your core impact will be certifying parametric conformance to **customer requirements** through rigorous electrical validation tests. This role offers the chance to work with cutting-edge **CXL, Ethernet, and PCIe technologies**.

You'll drive RTL to GDS ownership for Astera Labs' connectivity ASICs used by leading cloud providers. Your work will directly impact **full-chip signoff quality** and **design methodology enhancements**. This role stands out with exposure to **cutting-edge AI infrastructure** and **advanced node technologies**.

You'll define the **end-to-end architecture** for next-generation AI infrastructure at the epicenter of the AI revolution, spanning server firmware, high-speed connectivity, and rack-scale system design. Your core impact is directly enabling **hyperscale AI training and inference workloads** through purpose-built rack-scale platforms. This high-visibility role includes influencing **industry standards and mentoring senior architects**.

You'll own the **DFT architecture** and ensure the testability of chips that power the world's largest AI clusters. As a foundational member of a new R&D center, you'll drive **ATE pattern generation** and **post-silicon bring-up**. This role offers **meaningful product ownership** in a rapidly growing company.

You'll join the **Hardware Engineering team** to build diagnostics and manufacturing software for **high-speed datacenter products**. You'll work from conception to final production, enabling design, test, and **scale-out connectivity** for AI infrastructure.

You'll drive **RTL implementation** of complex digital designs for **AI connectivity solutions** at hyperscale. Your work will shape CPU subsystems and security architectures that power the world's most advanced data centers. This role offers a chance to influence the next generation of rack-scale AI infrastructure.

You'll oversee the physical design of **connectivity ASICs** used in the world's leading cloud service providers and server OEMs. Your core impact will be driving **block-level ownership from architecture to GDSII** for complex designs in sub-7nm technologies. You'll collaborate with designers, verification, and operations teams in a fully on-site role.

You'll be a key architect of our silicon's physical reality, owning the transformation of complex logic into high-performance silicon for **AI infrastructure connectivity**. You'll drive physical implementation from synthesis through signoff, ensuring extreme performance and power targets. This role offers meaningful product ownership in a new site.

You'll own **block-level physical design** for connectivity ASICs used in **hyperscaler AI infrastructure**. Your work drives chips from RTL to GDSII, collaborating with cross-functional teams to close timing and deliver to production.

You'll own **block-level physical design** from RTL to GDSII for connectivity ASICs used in **cloud-scale AI infrastructure**, collaborating with cross-functional teams. This role demands broad expertise in **floorplanning, place-and-route, timing closure, and signoff** for cutting-edge process nodes.

You'll lead firmware development for **data-center and AI infrastructure** SoCs and systems at a fast-growing NASAQ-listed company. You will own execution strategy, build and mentor high-performing teams, and partner closely with hardware, validation, and customers to deliver complex firmware programs.

You'll join the Hardware Engineering team to build diagnostics and manufacturing software for cutting-edge high-speed datacenter products. Your work will span from conception to production at contract manufacturers, **enabling design validation** and **mass production tests**. You'll collaborate with hardware engineers on bring-up schedules and feature delivery.

You'll operate **manual probe stations** and perform **DC/signal integrity measurements** on PCBs for AI infrastructure connectivity products. Your work directly supports engineering teams in developing world-class hardware. This contract role offers exposure to cutting-edge semiconductor technologies.

You'll work closely with firmware, system validation, and product teams to support **silicon bring-up** and **debug** through hands-on lab execution. Your core impact will be configuring test environments, **testing high-speed interfaces**, and managing RMA processes. This role offers the chance to contribute to AI infrastructure connectivity at a leading public company.

You'll lead a team of physical design engineers at our Toronto site, driving connectivity ASICs from RTL to GDSII. Your work will power **high-speed serial connectivity** solutions deployed in the world's largest AI clusters. You'll combine hands-on technical leadership with people management to build a high-performing team.

You'll lead development of next-generation high-speed semiconductor products in advanced process nodes. Your work will drive **AI infrastructure connectivity solutions** for hyperscale data centers. You'll collaborate with cross-functional teams to deliver **end-to-end product development** from concept to manufacturing.

You'll partner directly with leaders across Business and G&A functions as a trusted advisor on people strategy. Your core impact will drive organizational effectiveness, talent development, and leadership capability during hypergrowth. This role offers an opportunity to shape HR practices in a fast-scaling AI infrastructure company.

You'll join Astera Labs' Product Quality Engineering team to drive root-cause analysis of failures across circuit, package, firmware, and protocol layers for **PCIe and Ethernet connectivity solutions** that power AI infrastructure. You'll use **advanced lab instrumentation** to debug high-speed SERDES devices and accelerate failure analysis. This early-career role offers hands-on work with cutting-edge semiconductor technology in a fast-growing company.

You'll design **high-speed analog and mixed-signal circuits** for **next-generation transceiver IPs** at **TSMC 5/3nm nodes**. Your core impact is ensuring robust performance and successful silicon validation for wireline transceivers. You'll collaborate with layout, verification, and system teams to optimize for power and efficiency.

You'll lead the design and development of embedded firmware for **PCIe/CXL memory expansion products** tailored for AI and cloud infrastructure. Your work will enable next-generation memory devices powering high-performance computing platforms. This onsite role offers the opportunity to collaborate with hyperscalers on cutting-edge connectivity solutions.

You'll lead **go-to-market strategy** for Astera Labs' fabric switch and memory controller solutions, enabling **AI and cloud data centers**. You will shape narrative for technologies like PCIe, CXL, and UALink, driving **adoption by hyperscalers**.

You'll lead **strategic transactions** including acquisitions and partnerships in the **AI and cloud infrastructure space**. You'll work with cross-functional teams to identify opportunities that align with Astera Labs' growth strategy. This role offers high visibility and direct influence on strategic decisions at a hyper-growth company.

You'll join Astera Labs to manage **PCBA manufacturing** and **production testing** for AI connectivity solutions. Your work ensures high-quality, reliable hardware for hyperscaler clients. This role offers the chance to impact cutting-edge AI infrastructure.

You'll lead **functional verification** of complex ASICs for **AI infrastructure**, covering the full lifecycle from planning to coverage closure. You'll collaborate with software and system validation teams to execute test plans on emulation platforms.

You'll architect and implement **next-generation digital designs** for high-performance AI connectivity solutions at Astera Labs. You'll own complex blocks from micro-architecture through silicon bring-up, collaborating with verification and physical design teams. This role lets you work on **cutting-edge PCIe Gen 6/7, CXL, and UALink protocols** deployed by leading hyperscalers.

You'll join a team designing **power delivery systems** for cutting-edge AI infrastructure ASICs. Your work will ensure **stable voltage and current distribution** across boards. Collaborate with cross-functional teams using industry-leading tools to deliver high-performance solutions.

You'll **develop and perform system validation tests** for **AI fabric switch products** using leading-edge data center equipment and scalable automation platforms. You'll own product certification against customer system requirements and work directly with hyperscalers to highlight unique capabilities.

You'll **architect and develop firmware** for Astera Labs' SoC and systems products, with a focus on **PCIe-based embedded systems**. Your work enables major differentiating features, and you'll collaborate closely with customers to ensure their needs are met.

You'll partner directly with engineering organizations as a trusted advisor and coach, supporting talent strategies and organizational health. Your core impact will be enabling engineering teams to deliver world-class AI infrastructure products through effective people practices. This role is critical for scaling the company's people operations in a fast-paced AI infrastructure company.

You'll **own physical implementation** from RTL to GDSII for **next-generation transceiver IPs** at 5nm/3nm nodes, collaborating with cross-functional teams to ensure timing and power closure. Your work will directly impact **ultra-high-speed designs** powering AI infrastructure at Astera Labs.

You'll join the Hardware Electrical Validation team at Astera Labs, linking electrical design and validation teams. You'll **develop and execute validation plans** for PCBAs, debug complex failures, and **support system validation architectures**. This role is not post-silicon validation; it focuses on electrical validation of board-level hardware.

You'll architect methodologies and automation scripts that enable our hardware teams to push silicon performance limits. Your work directly impacts design productivity and time-to-market for **next-generation processors**. Join a new R&D center building the AI infrastructure backbone.

You'll lead the **AI Fabric Validation organization** at Astera Labs, ensuring **connectivity solutions perform at scale** for the most demanding AI workloads. Your team will validate silicon, firmware, and system-level solutions to achieve production readiness. This role offers deep insight into next-generation AI infrastructure platforms.

You'll validate **Taurus Ethernet Smart Cable Modules** and ASICs for **AI server platforms**. Your work ensures seamless connectivity in cutting-edge AI infrastructure. This role offers hands-on lab experience with high-speed interconnects.

You'll own **STA sign-off** for our AI connectivity chips, collaborating across architecture, design, and backend teams. Your work will directly impact **the performance of next-gen AI clusters** by ensuring rigorous timing closure. This role offers **ground-floor impact** at a new R&D center.

You'll lead **ATE test solutions** for complex mixed-signal SoC products at Astera Labs, a leader in rack-scale AI infrastructure. You own test strategy from design through high-volume production, collaborating with design teams and manufacturing partners. This role offers direct impact on cutting-edge **AI connectivity** technology with exposure to high-speed protocols like PCIe and Ethernet.

You'll own the journey from **high-level definition** through **micro-architecture and RTL implementation** to backend support for complex digital blocks that power AI clusters. You'll be part of a team defining the next generation of **AI infrastructure connectivity**. This is an opportunity to build our new Israel R&D center from the ground up.

You'll verify digital and mixed-signal designs for **high-speed Ethernet, UALink, and PCIe PHY** sub-blocks at a leading AI infrastructure company. You'll collaborate with architects and designers to develop comprehensive verification plans and **debug functional issues** to ensure product robustness.

You'll develop and maintain CAD tools and design flows for analog and mixed-signal IC design at a **purpose-built AI connectivity solutions** company. Your core impact is enabling design teams to achieve **efficient and robust design environments** by automating tasks and integrating PDKs. You'll collaborate closely with circuit designers, layout engineers, and EDA vendors to **improve design productivity**.

You'll join a talent pool for **future opportunities** at a company building **rack-scale AI infrastructure** solutions. We'll match your skills to upcoming roles in engineering, product, or operations.

You'll lead **package design engineering** for **AI infrastructure products** at Astera Labs. You'll own end-to-end delivery of advanced IC packaging solutions from architecture through production ramp, directly impacting **PCIe, CXL, and Ethernet connectivity** for hyperscale customers.

You'll play a pivotal role in identifying key data points, developing data collection strategies, and deriving actionable insights. You will **create automated data pipelines** and apply **AI techniques** to predict failures, collaborating with cross-functional teams to support decision-making at Astera Labs.

You'll contribute to **next-generation digital designs** for high-performance connectivity solutions at Astera Labs, working on complex blocks from micro-architecture through silicon bring-up. Your core impact will be owning RTL implementation and collaborating with verification and DFT teams. This role stands out for its focus on **AI infrastructure connectivity** in a fast-paced environment.

You'll support world-leading cloud service providers and server OEMs by designing solutions using Astera Labs' connectivity products. You'll identify customer requirements, propose solutions, and provide hands-on design-in support. You'll drive innovation by listening to customer needs and working with engineering teams.

You'll design and manage global benefits programs for a **hyper-growth AI infrastructure company**, partnering with HR leadership to attract and retain world-class talent. You'll drive **strategic benefits initiatives** across the US, Canada, Asia, and EMEA. This role offers the chance to shape programs at a **public company scaling rapidly**.

You'll execute SoC top-level physical design for chips driving the world's largest AI clusters, focusing on **implementation** and **tape-out GDS** meeting strict signoff criteria. You'll collaborate with architecture, design, and product teams to achieve optimal **PPA targets** for AI at scale.

You'll join a strategic R&D center in Israel to execute **EMIR power integrity** analysis and sign-off for high-performance connectivity silicon powering the world's largest AI clusters. You'll ensure power robustness and reliability in advanced FinFET nodes, directly impacting **AI infrastructure performance** at scale.

You'll lead **post-silicon product development** for **next-gen high-speed semiconductor products** at Astera Labs. Your work directly enables **AI and cloud infrastructure connectivity** solutions.

You'll **execute IC package design** for high-performance connectivity silicon powering AI clusters. You'll **drive package architecture and technology selection** to meet electrical, thermal, and cost targets. This role offers **meaningful product ownership** in a new R&D center.

You'll design and verify blocks for **high-performance compute and networking standards** using cutting-edge methodology and tools. You'll work on advanced CMOS process nodes as part of our ASIC team, collaborating with hyperscalers on **purpose-built connectivity solutions**.

You'll own engineering manufacturing and maintain smooth production for high-speed semiconductor products at OSAT partners. You'll ensure on-time customer shipments and drive seamless manufacturing during mass production. This role offers direct impact on **rack-scale AI infrastructure** for a **NASDAQ-listed company**.

You'll design **advanced node CMOS** mixed-signal circuits for **AI connectivity solutions**. Your circuits will power high-speed data transmission in **hyperscaler data centers**. This role offers hands-on work with cutting-edge SerDes technology.

You'll drive **operational cadence** and **execution rigor** as a force-multiplier for Engineering leadership, while leading **ASIC tapeout management** for silicon programs. Partner cross-functionally to align priorities and resolve blockers in a fast-paced AI infrastructure company.

You'll define **formal verification strategy** across Astera Labs' product portfolio for **PCIe Gen 6/7, CXL, Ethernet, and UALink** technologies. Your work will directly enable the rack-scale AI infrastructure transforming cloud computing worldwide.

You'll own end-to-end IC package design for high-performance connectivity silicon at a new R&D center in Israel. Your work will directly enable the world's largest AI clusters. This is a rare chance to **build a local engineering powerhouse** and take full product ownership from concept to production.

You'll lead **post-silicon bring-up** and **system validation** for PCIe/CXL memory expansion products used in AI data centers. You'll design validation plans, automate test flows, and collaborate with customers to ensure real-world performance. This role is based in our **Vancouver office**, a strategic growth hub with close ties to our San Jose team.

You'll design **high-speed mixed-signal circuits** for advanced node CMOS products at a **leading AI connectivity company**. Your work will directly impact scalable AI infrastructure deployments. This role offers hands-on tapeout experience and collaboration with top hyperscalers.

You'll drive end-to-end success of our next-generation UALink switching products, connecting architecture, design, validation, firmware, systems, and operations. Your work will **power the largest AI clusters in the world** and enable **rack-scale AI infrastructure** for hyperscalers.

You'll architect and develop firmware and microcontroller subsystems for Astera Labs' SoC products, enabling **AI infrastructure** connectivity. Your work directly impacts **differentiating product features** and involves customer-facing collaboration to ensure needs are met.

You'll design and execute functional, performance, and stress tests for **PCIe switch products** at a **leading AI connectivity company**. Your work directly enables robust connectivity solutions for hyperscale data centers. This role offers the chance to collaborate with top silicon, architecture, and firmware teams.

You'll design advanced node Bi-CMOS / CMOS products for **AI connectivity solutions** at a Nasdaq-listed company. Your work will directly impact **high-speed circuit performance** by minimizing parasitics and ensuring EM/IR compliance. You'll collaborate across time zones with a **dynamic cross-functional team**.

You'll join Astera Labs' Field Application Engineering team in Taipei, supporting **cloud service providers** and **server OEMs** in designing solutions using Astera Labs' connectivity products. You'll identify customer requirements, propose tailored solutions, and provide hands-on design-in support.

You'll validate **next-generation SoCs** for AI connectivity and cloud infrastructure on industry-leading emulation platforms. You will ensure functionality and performance before silicon tape-out, collaborating with cross-functional teams to define and execute validation plans. This role offers the chance to work with **high-speed serial interfaces** like PCIe, Ethernet, and UALink.