Partcl

You'll design **core intermediate representations** for physical-design tools and build **compiler-like pipelines** that transform design data across stages. You'll optimize for query latency, cache locality, and parallel traversal, directly impacting **chip design automation**.

You'll **explore new ML model architectures** for chip design, achieving **1000x performance improvements**. You'll architect end-to-end pipelines and **deploy directly with customers** in their offices. This is a rare opportunity to shape an early-stage startup from the ground up.