Fractile

You'll lead **manufacturing test solutions** for next-gen AI accelerator chips at a cutting-edge startup. Your core impact is ensuring robust, scalable production of high-performance silicon that redefines AI compute. You'll collaborate with top engineers on **first silicon bring-up through high-volume ramp**.

You'll drive the manufacturing test strategy for **AI accelerator chips** at Fractile, a fast-growing startup redefining AI hardware. Your core impact will be leading chip product engineers and external partners from DFT through high-volume ramp, ensuring robust and cost-effective test solutions for advanced AI accelerator platforms. This role stands out for its **full-stack engagement** across hardware, software, and silicon teams.

You'll **build tooling and workflows** around EDA tools at Fractile, a company creating hardware to overcome AI's memory bottleneck. Your work will **accelerate chip design cycles** and improve compute infrastructure. This role offers a chance to impact cutting-edge AI hardware.

You'll design and own **Bazel rules and extensions** for a fast-growing deep-tech company building new ML hardware and software. Your work will scale our monorepo across Python, C++, Rust, SystemVerilog and ML workloads, optimising CI performance and defining the developer experience for every engineer. This is a **greenfield Bazel role** with no legacy — you'll build the ecosystem from scratch.

You'll **own the Bazel monorepo** and **build build pipelines** for a deep-tech company redefining AI hardware. Your work will be the **backbone of the entire engineering organization**.

You'll serve as Fractile's technical representative at Taiwan-based foundry partners in a **fabless IC model**. You'll drive **yield ramp acceleration**, parametric performance tracking, and process integration alignment to deliver advanced AI silicon. This high-leverage role directly impacts cost, performance, and production scalability.

You'll build **developer tooling** for optimising large language models on **next-generation inference hardware** at Fractile. Your work will shape the APIs, documentation, and workflows that define the developer experience. This role offers a tight **hardware-software co-design loop** with world-class silicon and systems engineers.

You'll drive **full-chip physical implementation** from synthesis to sign-off for **next-generation AI chips** at a fast-growing startup. Your work directly enables **100x speed increases** for large language models.

You'll own Bazel at scale and build tooling powering ML models, kernel drivers, and hardware simulation. Your work becomes the backbone of the entire engineering organization, with no legacy and extreme variety across ML, compilers, and simulators.

You'll develop the ML compiler stack for Fractile's groundbreaking AI accelerators, enabling **industry-leading LLM performance**. Your work will be central to a full-stack execution engine rethinking computing from first principles.

You'll **integrate AI accelerators** with open-source projects like PyTorch and vLLM, and develop a **high-performance Rust runtime** in a collaborative hardware-software team. You'll work at the **cutting edge of AI hardware and software** to run large language models faster.

You'll own **packaging manufacturing execution** in Taiwan, driving products from first silicon through high-volume production at a startup redefining AI hardware. Your decisions on yield, ramp velocity, and supplier performance directly impact strategic momentum. This role combines deep technical authority in **advanced packaging** with the accountability of a senior leader in a fast-scaling environment.

You'll **design and develop the Linux kernel driver** for Fractile's ultra-fast AI inference chip, working at the boundary between host and silicon. Your work directly impacts **throughput and latency gains** on cutting-edge server platforms. You'll be there from pre-silicon simulations through first bring-up and end-to-end performance jumps.

You'll design and maintain the Linux kernel driver for Fractile's AI accelerator, working at the boundary between host and silicon. Your work will directly impact **throughput and latency gains** through performance-critical kernel-space paths. You'll collaborate in a tight co-design loop with hardware, firmware, and ML engineers **from pre-silicon simulations to first bring-up**.

You'll join a new team writing **Rust server-side software** for a greenfield AI inference stack, including a **Linux kernel driver**, to power the world's fastest AI chip. You'll research state-of-the-art AI inference and implement your ideas, shaping architecture from day one.

You'll write **Rust server-side software** to build a greenfield reference implementation of a full AI inference stack tailored to custom hardware. Your work will span from **Linux kernel drivers** to **cloud tooling**, directly influencing architecture from day one. You'll also conduct state-of-the-art research to optimize performance.

You'll build a functional simulator of Fractile's AI accelerator hardware, enabling software iteration before silicon exists. Your work will directly impact chip bring-up and team productivity by ensuring simulator fidelity. You'll collaborate across hardware and software teams in a fast-moving HW/SW co-design environment.

You'll define and drive the **end-to-end hardware architecture** for AI acceleration products, from chip-level interfaces through system integration. Your impact will be ensuring **coherent system-level performance** across hardware, firmware, and software. This hands-on role involves early prototyping and bring-up at a rapidly growing startup.

You'll support the **physical implementation** of complex ASIC/SoC designs at a **rapidly expanding AI hardware startup**. Your work will directly impact **performance, power, and area optimization** for next-generation chips enabling 100x speed increases for large language models.

You'll write performance-critical ML kernels in C and assembly for **AI inference chips**. Your work directly influences silicon trade-offs and system deployment. You'll drive **first accelerator compute runs** and feed results back into the hardware and software roadmap.

You'll define and drive the architecture of our core compute engines, **ISA definitions** and programming models through to memory hierarchies and on-chip interconnects. You'll work closely with teams to translate architectural intent into **working silicon** that performs in the real world. Expect to be hands-on in performance modelling and bottleneck analysis, ensuring every cycle counts.

You'll lead **physical design implementation** for next-generation AI chips at a pioneering hardware startup. Your core impact will be owning end-to-end chip design, from synthesis to sign-off, optimizing for performance, power, and area. This role offers **full-chip ownership** and collaboration with cross-functional teams.

You'll build the **control chain** that powers on, monitors, and secures rack-scale AI inference systems. Your work ensures **reliable production-critical firmware** from bring-up to deployment. This role has high ownership and deep impact on hardware-software co-design.

You'll take an active role in building world-class ML/AI IC products for **pre-silicon RTL verification**, collaborating across modelling, system architecture, and RTL design teams. Your core impact will be ensuring RTL releases meet the highest functional quality standards. This role stands out for its blend of hardware and software discipline in a rapidly growing startup.

You'll **develop and optimize RTL designs** for high-performance AI systems at a **fast-growing silicon startup**. Your work will directly impact the frontier of AI hardware, delivering **radically higher speed and lower cost** for advanced models.

You'll define and drive the **end-to-end hardware architecture** for AI acceleration products, from chip-level interfaces to system-level integration. You'll work closely with digital and verification teams to translate architecture into **working silicon and reliable hardware platforms** and be hands-on in prototyping and bring-up. This role offers full-stack engagement across hardware, software, and silicon teams.

You'll **own Bazel at scale** and build the tooling that powers every part of Fractile, from ML models to kernel drivers. This is a **greenfield opportunity** to shape the developer experience in a fast-growing deep-tech company. You'll work across Python, C++, Rust, SystemVerilog and ML workloads.

You'll be a key contributor to building world-class ML/AI IC products for data center applications. You will own **pre-silicon RTL verification** and collaborate across disciplines to ensure **high functional quality** in a fast-paced, ambitious environment.

You'll **verify RTL designs** for **AI/ML data center chips** at a fast-growing startup. Your work directly impacts tape-out quality and product speed. This role offers **broad exposure** across hardware and software disciplines.

You'll join a team building **silicon, systems and software** to redefine AI performance. You'll own verification for **ML/AI IC products** targeting data center scale-out. This role offers exposure across disciplines in a collaborative, fast-growing startup.

You'll lead the design of **advanced cooling architectures** for high-density AI accelerator systems. Your core impact will be developing production-ready cooling solutions from Direct-to-Chip liquid cooling through rack-level thermal management. This role stands out for its hands-on influence over the full thermal stack at a fast-growing AI hardware startup.

You'll own the architecture and execution of system-level test strategies for an **AI accelerator server platform**, covering manufacturing and field deployment. Your work ensures **scalable, reliable test processes** for high-volume production and in-field diagnostics. This role offers **full-stack engagement** across hardware, firmware, and software teams.

You'll write **performance-critical ML kernels** in C and assembly for a novel AI inference chip. Your work directly influences **hardware-software co-design** and silicon roadmaps. You'll drive **first accelerator compute runs** and feed results back into the architecture.

You'll define and drive the architecture of **compute engines** for AI acceleration at Fractile. Expect to be hands-on in performance modelling and detailed specification writing. You will work closely with logical design, physical design, and verification teams to translate architectural intent into working silicon that performs in the real world.

You'll **develop system-level hardware defect detection tests** for an AI accelerator server platform. Your work will ensure **fast and reliable identification of hardware issues** in factory and service environments. You'll collaborate across teams to implement tests that **cover PCIe, power, cooling, and interconnect faults**.

You'll join the team implementing **DFT for a large, multi-core AI accelerator ASIC**, working on scan, ATPG, and memory test. You'll contribute to a robust and scalable test solution while developing your expertise in advanced SoC design. This role offers high ownership and rapid iteration in a fast-growing startup.

You'll own **full-chip physical design** for next-gen AI accelerators, driving PPA optimisation and tape-out success. Your work will directly impact **100x speed improvements** for large language models. This role offers **full-chip ownership** and collaboration with cross-functional teams from RTL to foundry.

You'll deliver **complex, high-speed and high-power PCB designs** while owning PCB library creation and validation. Your work will directly impact **electrical performance and manufacturability** across multiple products. This role combines deep layout expertise with **library governance best practices**.

You'll drive end-to-end physical implementation of **next-generation AI chip designs** at **Fractile**, contributing to full-chip ownership from synthesis to sign-off. You'll collaborate with cross-functional teams to optimize PPA while ensuring design integrity. This role offers the chance to work with **advanced AI tools and models** to enhance productivity and design quality.

You'll build a functional simulator of Fractile's AI accelerator hardware, enabling software teams to iterate before silicon exists. Your work will unblock cross-team debugging and shape silicon decisions through simulator fidelity. **This role combines low-level hardware modeling** with **large-scale distributed simulation**.

You'll build **control chain software** for Fractile's AI inference chips, working on bare metal, RTOS, and embedded Linux. Your work ensures **rack-scale systems are stable, safe, and secure**. This is a critical layer between silicon and reliable output at scale.

You'll drive **AI accelerator board** industrialization from EVT to mass production, working at the intersection of hardware design and manufacturing engineering. Your core impact will be **shaping how Fractile scales hardware manufacturing** through close partnership with Taiwan-based PCB fabs and SMT partners.

You'll develop production-ready manufacturing test solutions for an advanced **AI accelerator chip**. Core impact: enabling **high-volume manufacturing** of silicon that redefines AI performance. Collaborate closely with design, DFT, and product engineering teams.

You'll design and implement production-ready **board test solutions** for high-volume AI accelerator boards with **PCIe Gen6 interconnect**. Your work will enable reliable manufacturing at offshore partners.

You'll design and implement **RTL designs** for high-performance, power-efficient AI silicon at a **fast-growing startup**. You'll collaborate across teams to optimize performance, power, and area. This role offers exposure to the full project lifecycle and a culture that values your ideas.

You'll develop **pre‑silicon models** of Fractile's AI accelerator hardware, enabling **architectural exploration** and **early software development**. Your models will directly shape performance, trade‑offs, and product lifecycle.

You'll contribute to **next-generation chip designs** at Fractile, pioneering AI innovation with x100 speed increases. Your core impact will be supporting the implementation of complex IC physical designs from synthesis to sign-off. You'll collaborate across teams to **optimise performance, power, and area** while ensuring design integrity.

You'll lead the **manufacturing test strategy** for an advanced AI accelerator chip program, managing both internal teams and subcontractors. Your work will ensure **high-quality, high-volume test solutions** for cutting-edge silicon. This role offers the chance to shape test architecture across **digital, memory, and high-speed interfaces**.

You'll develop and optimize **RTL designs** for high-performance AI systems at Fractile, a fast-growing silicon startup. Your work will directly enable running the world's most advanced models at radically higher speed and lower cost. You'll collaborate across hardware and software teams to deliver a product with generational impact.

You'll develop the **machine learning compiler stack** for Fractile's innovative AI acceleration hardware, enabling industry-leading performance of the latest LLMs. You'll collaborate with hardware, driver runtime, and ML engineers in a highly collaborative hardware-software co-design methodology. This role offers a rare opportunity to shape the compiler architecture from first principles.

You'll integrate Fractile's AI acceleration hardware with open source projects like **PyTorch** and **vLLM**, and develop our high-performance **Rust runtime**. This role is at the cutting edge of AI hardware-software co-design.

You'll develop **pre-silicon models** of Fractile's AI accelerator, enabling architectural exploration and performance analysis. Your models will **shape hardware architecture** and unblock software teams months before silicon exists. This is a high-leverage role in a hardware-software co-design loop.

You'll **define the DFT architecture** for a large, multi-core AI accelerator SoC, taking ownership from early strategy through silicon bring-up. Your work will directly enable **scalable, power-aware test solutions** for the world's most advanced AI models. This role combines architectural leadership with hands-on execution.

You'll **develop and optimize RTL designs** for high-performance AI silicon, **contributing across the full project lifecycle**. This role offers **exposure to a broad range of disciplines** in a collaborative, growing team.

You'll manage silicon production, packaging design, and delivery flow for AI chips at Fractile. Your work directly enables **high-performance AI model deployment** through tight coordination with foundries and OSAT partners. This role offers **ownership of end-to-end hardware delivery** in a fast-growing deep-tech startup.